ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
The FPD-Link III receiver also checks the decoded data for encoding or sequence errors in the received FPD-Link III frame. If either of these error conditions are detected the FPD3_ENC_ERROR bit will be latched in the RX_PORT_STS2 register 0x4E[5] (see Table 7-92). An interrupt may also be generated based on assertion of the encoded error flag. To detect FPD-Link III Encoder errors, the LINK_ERROR_COUNT must be enabled with a LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock will prevent detection of the Encoder error. The FPD3_ENC_ERROR flag is cleared on read.
When partnered with a DS90UB633A-Q1 the FPD3 Encoder may be configured to include a CRC check of the FPD3 encoder sequence. The CRC check provides an extra layer of error checking on the encoder sequence. This CRC checking adds protection to the encoder sequence used to send link information comprised of Datapath Control registers 0x59 (Table 7-103) and 0x5A (Table 7-104), Sensor Status registers 0x51 - 0x54 (Table 7-95 through Table 7-98), and Serializer ID register 0x5B (Table 7-106). TI recommends that designers enable CRC error checking on the FPD3 Encoder sequence to prevent any updates of link information values from encoded packets that do not pass CRC check. The FPD3 Encoder CRC is enabled by setting the FPD3_ENC_CRC_DIS register 0xBA[7] to 0 (see Table 7-172). In addition, the FPD3_ENC_CRC_CAP flag should be set in register 0x4A[4] (see Table 7-88).