ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
The AEQ circuit can be restarted at any time by setting the AEQ_RESTART bit in the AEQ_CTL2 register 0xD2 (see Table 7-181). When the deserializer is powered on, the AEQ is continually searching through the EQ settings and could be at any setting when the serializer supplies a signal. If the Rx Port CDR locks to the signal, it may be acceptable for low bit errors, but it may not optimized or overequalized. When connected to a compatible serializer (DS90UB633A-Q1 or DS90UB63x CSI-2 Serializer), the DS90UB662-Q1 will restart the AEQ adaption by default after the device achieves the first positive lock indication to supply a more consistent start-up from known conditions.
With this feature disabled, the AEQ may lock at a relatively random EQ setting based on when the FPD-Link III input signal is initially present. Alternatively, AEQ_RESTART or DIGITAL_RESET0 can be applied once the compatible serializer input signal frequency is stable to restart adaption from the minimum EQ gain value. These techniques allow for a more consistent initial EQ setting following adaption.