ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
RX port-specific register. The FPD-Link III Port Select register 0x4C configures which unique Rx port registers can be accessed by I2C read and write commands.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7 | LINE_LEN_UNSTABLE | R/RC | 0 | Line Length Unstable If set, this bit indicates the line length was detected as unstable during a previous video frame. The line length is considered to be stable if all the lines in the video frame have the same length. This flag will remain set until read. |
| 6 | LINE_LEN_CHG | R/RC | 0 | Line Length Changed 1: Change of line length detected 0: Change of line length not detected This bit is cleared on read. |
| 5 | FPD3_ENCODE _ERROR | R/RC | 0 | FPD3 Encoder error detected If set, this flag indicates an error in the FPD-Link III encoding has been detected by the FPD-Link III receiver. This bit is cleared on read. Note, to detect FP3 Encoder errors, the LINK_ERROR_COUNT must be enabled with a LINK_ERR_THRESH value greater than 1. Otherwise, the loss of Receiver Lock will prevent detection of the Encoder error. |
| 4 | BUFFER_ERROR | R/RC | 0 | Packet buffer error detected. If this bit is set, an overflow condition has occurred on the packet buffer FIFO. 1: Packet Buffer error detected 0: No Packet Buffer errors detected This bit is cleared on read. |
| 3 | CSI_ERROR | R | 0 | CSI-2 Receive error detected See the CSI_RX_STS register for details. |
| 2 | FREQ_STABLE | R | 0 | Frequency measurement stable |
| 1 | NO_FPD3_CLK | R | 0 | No FPD-Link III input clock detected |
| 0 | LINE_CNT_CHG | R/RC | 0 | Line Count Changed 1: Change of line count detected 0: Change of line count not detected This bit is cleared on read. |