ZHCSMR3A november 2020 – november 2020 DS90UB633A-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | PIN / FREQ | MIN | NOM | MAX | UNIT | |
|---|---|---|---|---|---|---|---|
| tTCP | Transmit clock period | 10-bit mode 75 MHz – 100 MHz | 10 | T | 13.33 | ns | |
| 12-bit mode 56.25 MHz - 100 MHz | 10 | T | 17.78 | ns | |||
| tTCIH | Transmit clock input high time | 0.4T | 0.5T | 0.6T | |||
| tTCIL | Transmit clock input low time | 0.4T | 0.5T | 0.6T | |||
| tCLKT | PCLK input transition time (Figure 6-7) | 10-bit mode 75 MHz – 100 MHz | 0.05T | 0.25T | 0.3T | ||
| 12-bit mode 56.25 MHz – 100 MHz | 0.05T | 0.25T | 0.3T | ||||
| tJIT0 | PCLK input jitter (3) (PCLK from imager mode) | LPF = ?/20, CDR PLL Loop BW = ?/15, BER = 1E-10 | ?PCLK = 56.25 – 100 MHz(5) | 0.45 | UI | ||
| tJIT1 | PCLK input jitter(3) (External oscillator mode) | LPF = ?/20, CDR PLL Loop BW = ?/15, BER = 1E-10 | ?PCLK = 56.25 – 100 MHz(5) | 1T | |||
| tJIT2 | External oscillator jitter(3)(4) | LPF = ?/20, CDR PLL Loop BW = ?/15, BER = 1E-10, paired with DS90UB662-Q1 deserializer | ?OSC = 37.5 – 66.67 MHz(6) | 0.45 | UI | ||
| ΔOSC | External Oscillator Frequency Stability | ?OSC = 37.5 – 66.67 MHz(6) | ±50 | ppm | |||
| tDC | CLKOUT duty cycle (external oscillator mode) | ?OSC = 37.5 – 66.67 MHz(6) | 45% | 50% | 55% | ||