ZHCSMR3A november 2020 – november 2020 DS90UB633A-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| LVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS) | |||||||
| VIH | High level input voltage | VIN = 3 V to 3.6 V | 2 | VIN | V | ||
| VIL | Low level input voltage | VIN = 3 V to 3.6 V | GND | 0.8 | V | ||
| IIN | Input current | VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V | –20 | ±1 | 20 | μA | |
| VOH | High level output voltage | V(VDDIO) = 3 V to 3.6 V, IOH = ?4 mA | 2.4 | V(VDDIO) | V | ||
| VOL | Low level output voltage | V(VDDIO) = 3 V to 3.6 V, IOL = 4 mA | GND | 0.4 | V | ||
| IOS | Output short-circuit current | VOUT = 0 V | Serializer GPO outputs | –15 | mA | ||
| IOZ | Tri-state output current | PDB = 0 V, VOUT = 0 V or V(VDDIO) | Serializer GPO outputs | –20 | 20 | μA | |
| CGPO | Pin capacitance | GPO [3:0] | 1.5 | pF | |||
| LVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS) | |||||||
| VIH | High level input voltage | VIN = 1.71 V to 1.89 V | 0.65 VIN | VIN | V | ||
| VIL | Low level input voltage | VIN = 1.71 V to 1.89 V | GND | 0.35 VIN | |||
| IIN | Input current | VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V | –20 | ±1 | 20 | μA | |
| VOH | High level output voltage | V(VDDIO) = 1.71 V to 1.89 V, IOH = ?4 mA | V(VDDIO) – 0.45 | V(VDDIO) | V | ||
| VOL | Low level output voltage | V(VDDIO) = 1.71 V to 1.89 V IOL = 4 mA | GND | 0.45 | V | ||
| IOS | Output short-circuit current | VOUT = 0 V | Serializer GPO outputs | –11 | mA | ||
| IOZ | Tri-state output current | PDB = 0 V, VOUT = 0 V or V(VDDIO) | Serializer GPO outputs | –20 | 20 | μA | |
| CGPO | Pin capacitance | GPO [3:0] | 1.5 | pF | |||
| IIN_STRAP | Strap pin input current | VIN = 0 V to VDD_n | MODE, IDX | –1 | 1 | μA | |
| LVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS) | |||||||
| VIH | High level input voltage | VIN = 2.52 V to 3.08 V | 0.7 VIN | VIN | V | ||
| VIL | Low level input voltage | VIN = 2.52 V to 3.08 V | GND | 0.3 VIN | |||
| IIN | Input current | VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V | –20 | ±1 | 20 | μA | |
| VOH | High level output voltage | V(VDDIO) = 2.52 V to 3.08 V, IOH = ?4 mA | V(VDDIO) - 0.4 | V(VDDIO) | V | ||
| VOL | Low level output voltage | V(VDDIO) =2.52 V to 3.08V IOL = 4 mA | GND | 0.4 | V | ||
| IOS | Output short-circuit current | VOUT = 0 V | Serializer GPO outputs | –11 | mA | ||
| IOZ | Tri-state output current | PDB = 0 V, VOUT = 0 V or V(VDDIO) | Serializer GPO outputs | –20 | 20 | μA | |
| CGPO | Pin capacitance | GPO [3:0] | 1.5 | pF | |||
| CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–) | |||||||
| VOD | Differential output voltage | RL = 100 ? (Figure 6-6) | 640 | 824 | mV | ||
| VOUT | Single-ended output voltage | RL = 50 ? (Figure 6-6) | 320 | 412 | |||
| ΔVOD | Differential output voltage unbalance | RL = 100 ? | 1 | 50 | mV | ||
| VOS | Output offset voltage | RL = 100 ? (Figure 6-6) | V(VDD_n) – (VOD /2) | V | |||
| ΔVOS | Offset voltage unbalance | RL = 100 ? | 1 | 50 | mV | ||
| IOS | Output short-circuit current | DOUT+ = 0 V or DOUT– = 0 V | –26 | mA | |||
| RT | Differential internal termination resistance | Differential across DOUT+ and DOUT– | 80 | 100 | 120 | ? | |
| Single-ended termination resistance | DOUT+ or DOUT– | 40 | 50 | 60 | |||
| SERIALIZER SUPPLY CURRENT | |||||||
| IDDT | Serializer (Tx) V(VDD_n) supply current (includes load current) | RL = 100 ? WORST CASE pattern (Figure 6-2) | V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V ? = 100 MHz, 12-bit mode Default registers | 76 | 95 | mA | |
| V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V ? = 75 MHz, 12-bit mode Default registers | 61 | 80 | mA | ||||
| IDDT | Serializer (Tx) V(VDD_n) supply current (includes load current) | RL = 100 ? RANDOM PRBS-7 pattern | V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V ? = 100 MHz, 12-bit mode Default Registers | 80 | mA | ||
| V(VDD_n) = 1.89 V V(VDDIO) = 3.6 V ? = 75 MHz, 12-bit mode Default Registers | 64 | ||||||
| I(VDDIO)T | Serializer (Tx) V(VDDIO) supply current (includes load current) | RL = 100 ? WORST CASE pattern (Figure 6-2) | V(VDDIO) = 1.89 V ? = 75 MHz, 12-bit mode Default Registers | 1.5 | 3 | mA | |
| V(VDDIO) = 3.6 V ? = 75 MHz, 12-bit mode Default registers | 5 | 8 | |||||
| IDDTZ | Serializer (Tx) supply current power down | PDB = 0 V; All other LVCMOS inputs = 0 V | V(VDDIO)=1.89 V Default registers | 300 | 1000 | μA | |
| V(VDDIO) = 3.6 V Default registers | 300 | 1000 | μA | ||||
| I(VDDIO)TZ | Serializer (Tx) V(VDDIO) supply current power down | PDB = 0 V; All other LVCMOS inputs = 0 V | V(VDDIO) = 1.89 V Default registers | 15 | 100 | μA | |
| V(VDDIO) = 3.6 V Default registers | 15 | 100 | μA | ||||