Transition of the PDB pin from LOW to HIGH must occur after the V_VDDIO and V_{VDD_n} supplies have reached their required operating voltage levels. Direct control of the PDB timing by processor GPIO is recommended if possible. When direct control of PDB is not available, the PDB pin can be tied to the power supply rail with an RC filter network to help ensure proper power up timing. GPO2 should be low when PDB goes high. Timing constraints are noted in Figure 8-1 and Table 8-1. Please refer to Section 7.3.8 for device operation when powered down.

If GPO2 state is not determined when PDB goes high, DS90UB633A-Q1 registers must be programmed to configure the transmission mode. Mode Select register 0x05[5] must be set to 1 and register 0x05 bit 1 and 0 are to be selected based on desired 12-bit or 10-bit transmit data format.

Common applications tie the V_(VDDIO) and V_{(VDD_n)} supplies to the same power source of 1.8 V typically. This is an acceptable method for ramping the V_(VDDIO) and V_{(VDD_n)} supplies. The main constraint here is that the V_{(VDD_n)} supply does not lead in ramping before the V_(VDDIO) system supply. This is noted in Figure 8-1 with the requirement of t₁ ≥ 0. V_(VDDIO) must reach the expected operating voltage earlier than V_{(VDD_n)} or at the same time.

Figure 8-1 Suggested Power-Up Sequencing

* If timing constraint t₃ cannot be assured, the following programming steps should be issued to the DS90UB633A-Q1 via local I2C control (not via remote back channel). These programming steps should be completed > 10ms after the power sequence is complete (V_PDB > PDB V_IH) with no delay between write commands. This step will cause a brief restart of the forward channel output:

• Write Register 0x27 = 0x28
• Write Register 0x27 = 0x20
• Write Register 0x27 = 0x00