ZHCSMR3A november 2020 – november 2020 DS90UB633A-Q1
PRODUCTION DATA
Figure 6-1 Bidirectional Control Bus Timing
Figure 6-2 “Worst Case” Test Pattern for Power Consumption
Figure 6-3 Serializer CML Output Load and Transition Times
Figure 6-4 Measurement Setup Serializer CML Output Load and Transition Times
Figure 6-5 Serializer VOD Setup
Figure 6-6 Serializer VOD Diagram
Figure 6-7 Serializer Input Clock Transition Times
Figure 6-8 Serializer Setup/Hold Times
Figure 6-9 Serializer PLL Lock Time
Figure 6-10 Serializer Delay