ZHCSMR3A november 2020 – november 2020 DS90UB633A-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| tLHT | CML low-to-high transition time | RL = 100 ? Figure 6-1 | 150 | 330 | ps | ||
| tHLT | CML high-to-low transition time | RL = 100 ? Figure 6-1 | 150 | 330 | ps | ||
| tDIS | Data input Setup to PCLK | Serializer data inputs Figure 6-8 | 2 | ns | |||
| tDIH | Data input Hold from PCLK | 2 | ns | ||||
| tPLD | Serializer PLL lock time.(1)(2) | RL = 100 ? Figure 6-9 | 1 | 2 | |||
| tSD | Serializer delay(2) | RT = 100 ?, 10–bit mode Register 0x03h b[0] (TRFB = 1) Figure 6-10 | 32.5T | 38T | 44T | ||
| RT = 100 ?, 12–bit mode Register 0x03h b[0] (TRFB = 1) Figure 6-10 | 11.75T | 13T | 15T | ||||
| tJIND | Serializer output deterministic jitter(3)(4)(5) | PRBS-7 test pattern, CDR PLL Loop BW = ?/15, BER = 1E-10 | DOUT± | 0.17 | UI | ||
| tJINR | Serializer output random jitter(3)(4)(5) | PRBS-7 test pattern, CDR PLL Loop BW = ?/15, BER = 1E-10 | DOUT± | 0.016 | UI | ||
| tJINT | Peak-to-peak serializer output total jitter(3)(5)(6) | PRBS-7 test pattern, CDR PLL Loop BW = ?/15, BER = 1E-10 | DOUT± | 0.4 | UI | ||
| λSTXBW | Serializer jitter transfer function –3 dB bandwidth | 10–bit mode PCLK = 100 MHz, Default registers | 2.2 | MHz | |||
| 12–bit mode PCLK = 100 MHz, Default registers | 2.2 | ||||||
| δSTX | Serializer jitter Transfer Function (peaking) | 10–bit mode PCLK = 100 MHz, Default registers | 1.06 | dB | |||
| 12–bit mode PCLK = 100 MHz, Default registers | 1.09 | ||||||
| δSTXf | Serializer jitter transfer function (peaking frequency) | 10–bit mode PCLK = 100 MHz, Default registers | 400 | kHz | |||
| 12–bit mode PCLK = 100 MHz, Default registers | 500 | ||||||