ZHCSME1C August 2018 – June 2021 DS250DF230
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Device Data Path Operation
- 8.3.2 Signal Detect
- 8.3.3 Continuous Time Linear Equalizer (CTLE)
- 8.3.4 Variable Gain Amplifier (VGA)
- 8.3.5 Cross-Point Switch
- 8.3.6 Decision Feedback Equalizer (DFE)
- 8.3.7 Clock and Data Recovery (CDR)
- 8.3.8 Calibration Clock
- 8.3.9 Differential Driver With FIR Filter
- 8.3.10 Debug Features
- 8.3.11 Interrupt Signals
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Electrostatic Discharge Caution
- 14術語表
- 15Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- RTV|32
訂購信息
9.2.1.3 Application Curves
Figure 9-5 shows a typical output eye diagram for the DS250DF230 operating at 25.78125 Gbps with PRBS9 pattern using FIR main-cursor of +28, pre-cursor of 0 and post-cursor of +3. All other device settings are left at default.
Figure 9-6 shows an example of DS250DF230 FIR transmit equalization while operating at 25.78125 Gbps. In this example, the Tx FIR filter main-cursor is set to +25, post-cursor to –3 and pre-cursor to –3. An 8T pattern is used to evaluate the FIR filter, which consists of 0xFF00. All other device settings are left at default.
Figure 9-5 DS250DF230 Operating at 25.78125 Gbps
Figure 9-6 DS250DF230 FIR Transmit Equalization While Operating at 25.78125 Gbps