ZHCS810H January 2012 – February 2018 DS125DF410
PRODUCTION DATA.
Register 0x18, bit 2
Normally the rise and fall times of the output driver of the DS125DF410 are set by the slew rate of the output transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by a system.
Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal. Setting this bit will approximately double the nominal rise and fall times of the DS125DF410 output driver. This bit is cleared by default.