ZHCS810H January 2012 – February 2018 DS125DF410
PRODUCTION DATA.
REFCLK_OUT pin 42 is the reference clock output pin. The DS125DF410 drives a buffered replica of the 25 MHz reference clock input on this output pin. If there are multiple DS125DF410 in the system, the REFCLK_OUT pin can be directly connected to the REFCLK_IN pin of another DS125DF410 in a daisy chain connection. The number of devices cascaded in a REF_CLK daisy chain is affected by the effective capacitance of the board trace connecting the REFCLK_OUT of one device to the REF_IN of the next device. The pulse high duration at the input of the last device must be greater than 4ns for proper operation.
In cases of cascading daisy chain with short trace (around 1.5 inches or 5pf trace capacitance), it is possible to cascade up to 9 devices. In other systems with longer interconnecting trace or more capacitive loading, the max number of daisy chained devices would be smaller. In a system which requires longer daisy chain, it is recommended to place an inverted gate after the 6th device. the pre-distorted duty cycle from the inverter allows for longer daisy chain. a better approach is to break the long daisy chain into two shorter chains, each driven by a buffer version of the clock and with each chain kept to a maximum of 6. As an example, if there are 12 devices in the system, the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for the reference clock output to input connection should be 1.5 inch or less.