日韩av无码中文无码下载,任你躁XXXXX麻豆精品,无码av深夜观看

ZHCS810H January 2012 – February 2018 DS125DF410

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RHS|48
- MPQF159B

散熱焊盤機械數據 (封裝 | 引腳)

RHS|48
- QFND509A

訂購信息

6.5 Electrical Characteristics

over recommended operating supply and temperature ranges with default register settings unless otherwise specified⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER
PD	Power Supply Consumption	Average power consumption (DFE powered-up and enabled)⁽²⁾		720		mW
PD	Power Supply Consumption	Max transient power supply current⁽³⁾		500	610	mA
NT_PS	Supply Noise Tolerance⁽⁴⁾	50 Hz to 100 Hz		100		mV_P-P
		100 Hz to 10 MHz		40		mV_P-P
		10 MHz to 5.0 GHz		10		mV_P-P
2.5V LVCMOS DC SPECIFICATIONS
V_IH	High Level Input Voltage		1.75		V_DD	V
V_IH	High Level (ADDR[3:0] pins)		2.28		V_DD
V_IL	Low Level Input Voltage		GND		0.7	V
V_IL	Low Level Input Voltage (ADDR[3:0] pins)		GND		0.335
V_OH	High Level Output Voltage	I_OH = -3 mA	2.0			V
V_OL	Low Level Output Voltage	I_OL = 3 mA			0.4	V
I_IN	Input Leakage Current	V_IN = V_DD			10	μA
I_IN	Input Leakage Current	V_IN = GND	–10			μA
I_IH	Input High Current (EN_SMB pin)	V_IN = V_DD		+55		μA
I_IL	Input Low Current (EN_SMB pin)	V_IN = GND		-110		μA
3.3 V LVCMOS DC SPECIFICATIONS (SDA, SDC, INT)
V_IH	High Level Input Voltage	V_DD = 2.5 V	1.75		3.6	V
V_IL	Low Level Input Voltage	V_DD = 2.5 V	GND		0.7	V
V_OL	Low Level Output Voltage	I_PULLUP = 3 mA			0.4	V
I_IH	Input High Current	V_IN = 3.6 V, V_DD = 2.5 V	20		40	μA
I_IL	Input Low Current	V_IN = GND, V_DD = 2.5 V	–10		10	μA
f_SDC	SMBus clock rate	Slave Mode	100		400	kHz
f_SDC	SMBus clock rate	Master Mode⁽⁵⁾		400		kHz
DATA BIT RATES
R_B	Bit Rate Range		9.8		12.5	Gbps
SIGNAL DETECT
SDH	Signal Detect ON Threshold Level	Default input signal level to assert signal detect, 10.3125 Gbps, PRBS-31		70		mV_p-p
SDL	Signal Detect OFF Threshold Level	Default input signal level to de-assert signal detect, 10.3125 Gbps, PRBS-31		10		mV_p-p
RECEIVER INPUTS (RXPn, RXNn)
V_{TX2, min}	Minimum Source Transmit Launch Signal Level (IN, diff)	See ⁽⁶⁾		600		mV_P-P
V_{TX2, max}		See ⁽⁶⁾		1000		mV_P-P
V_{TX1, max}		See ⁽⁷⁾		1200		mV_P-P
V_{TX0, max}		See ⁽⁸⁾		1600		mV_P-P
L_RI	Maximum Differential Input Return Loss - \|SDD11\|	100 MHz – 6 GHz		–15		dB
Z_D	Differential Input Impedance	100 MHz – 6 GHz		100		Ω
Z_S	Single-Ended Input Impedance	100 MHz – 6 GHz		50		Ω
DRIVER OUTPUTS (TXPn, TXNn)
V_OD0	Differential output voltage	Differential measurement with OUT+ and OUT- terminated by 50 Ω to GND, AC-Coupled, SMBus register VOD control (Register 0x2d bits 2:0) set to 0, minimum VOD De-emphasis control set to minimum (0 dB)	400		675	mV_P-P
V_OD7	Differential output voltage	Differential measurement with OUT+ and OUT- terminated by 50 Ω to GND, AC-Coupled SMBus register VOD control (Register 0x2d bits 2:0) set to 7, maximum VOD De-emphasis control set to minimum (0 dB)	1000			mV_P-P
V_{OD_DE}	De-emphasis level⁽¹⁰⁾	Differential measurement with OUT+ and OUT- terminated by 50 Ω to GND, AC-Coupled Set by SMBus register control to maximum de-emphasis setting Relative to the nominal 0 dB de-emphasis level set at the minimum de-emphasis setting		–15		dB
t_R, t_F	Transition time (rise and fall times)⁽¹⁰⁾⁽¹¹⁾	Transition time control = Full Slew Rate		39		ps
t_R, t_F	Transition time (rise and fall times)⁽¹⁰⁾⁽¹¹⁾	Transition time control = Limited Slew Rate		50		ps
L_RO	Maximum Differential Output Return Loss - \|SDD22\|	100 MHz – 6 GHz⁽⁹⁾		–15		dB
t_DP	Propagation Delay	Retimed data		300		ps
T_DE	De-emphasis pulse duration⁽¹²⁾	Measured at V_OD = 1000 mV_P-P, de-emphasis setting = -12 dB		75		ps
TJ	Output total jitter	Measured at BER = 10^-12⁽¹³⁾		10		ps
T_SKEW	Intra Pair Skew	Difference in 50% crossing between TXPn and TXNn for any output		3		ps
T_SKEW	Channel-to-Channel Skew			7		ps
CLOCK AND DATA RECOVERY
BW_PLL	PLL Bandwidth, -3 dB	Measured at 10.3125 Gbps		5		MHz
J_TOL	Input sinusoidal jitter tolerance 10 kHz to 250 MHz sinusoidal jitter frequency	Measured at BER = 10^-15		0.6		UI
J_TRANS	Jitter Transfer Sinusoidal jitter at 10 MHz jitter frequency	Measured at BER = 10^-15		–6		dB
T_LOCK	CDR Lock Time, Ref_mode 3, Fixed Data Rate (eg. 10.3125 Gbps)	Fixed (manual setting) of CTLE, DFE HEO/VEO lock monitor disabled (register 0x3e, bit 7 set to 0)		2		ms
		Fixed (manual setting) of CTLE, DFE HEO/VEO lock monitor enabled (register 0x3e, bit 7 set to 1 - default)		12		ms
		Medium (20 inch) channel loss with CTLE and DFE adaption, HEO/VEO lock monitor must be enabled ⁽¹⁴⁾		74		ms
TEMP_LOCK	CDR Lock, Ref_mode 3, 12.5Gbps	Parameter tested within -40°C to +85°C ambient range		100		°C
RECOMMENDED REFERENCE CLOCK SPECIFICATIONS
REF_f	Input reference clock frequency		24.9975	25	25.0025	MHz
REFCLK_IN_PW	Minimum REFCLK_IN Pulse Width	At REFCLK_IN pin		4		ns
REFCLK_OUT_DCD	REFCLK_OUT duty cycle distortion	C_L = 5 pF		0.55		ns
REF_VIH	Reference clock input min high threshold			1.75		V
REF_VIL	Reference clock input max low threshold			0.7		V

(1) Typical values represent most likely parametric norms at V_DD = 2.5V, T_A = 25°C., and at the Recommended Operation Conditions at the time of product characterization.

(2) V_DD= 2.5V, T_A = 25°C. All four channels active and locked. DFE is powered-up and enabled.

(3) Max momentary power supply current lasting less than 1s. The retimer may consume more power than the maximum average power rating during the time required to acquire CDR lock.

(4) Allowed supply noise (mV_P-P sine wave) under typical conditions.

(5) EEPROM device used for Master mode programming must support f_SDC greater than 400kHz.

(6) Differential signal amplitude at the transmitter output providing < 1x10^-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 40-inch long FR-4 stripline, 4-mil trace width.

(7) Differential signal amplitude at the transmitter output providing < 1x10^-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. Input transmission channel is 30-inch long FR-4 stripline, 4-mil trace width.

(8) Differential signal amplitude at the transmitter output providing < 1x10^-12 bit error rate. Measured at 10.3125 Gbps with a PRBS-31 data pattern. No input transmission channel.

(9) Measured with 10 MHz clock pattern output.

(10) Measured with clock-like {11111 00000} pattern.

(11) Slew rate is controlled by SMBus register settings.

(12) De-emphasis pulse width varies with V_OD and de-emphasis settings.

(13) Typical with no output de-emphasis, minimum output transmission channel.

(14) The CDR lock time is when the input has a valid signal to when the output sends retimed data. The CDR lock time is after the CTLE adaption is completed. In adapt_mode 2 or 3, the DFE adaption will continue after the CDR lock time.