ZHCS276F September 2011 – February 2025 DRV8818
PRODUCTION DATA
When the SLEEPn pin is low, the device enters a low-power sleep mode. In sleep mode all the internal MOSFETs are disabled (Hi-Z) and the internal logic regulator, charge pump, and internal clocks are all disabled. The tSLEEP time must elapse after a falling edge on the SLEEPn pin before the device enters sleep mode. The device is brought out of sleep automatically if the SLEEPn pin is brought high. The tWAKE time must elapse before the device is ready for inputs.