ZHCSIN3A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R
PRODUCTION DATA.
The CSA control register is shown in Figure 61 and described in Table 18.
Register access type: Read/Write
This register is only available with the DRV8353x family of devices.
| 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CSA
_FET |
VREF
_DIV |
LS
_REF |
CSA
_GAIN |
DIS
_SEN |
CSA
_CAL_A |
CSA
_CAL_B |
CSA
_CAL_C |
SEN
_LVL |
||
| R/W-0b | R/W-1b | R/W-0b | R/W-10b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-11b | ||
| Bit | Field | Type | Default | Description |
|---|---|---|---|---|
| 10 | CSA_FET | R/W | 0b |
0b = Sense amplifier positive input is SPx 1b = Sense amplifier positive input is SHx (also automatically sets the LS_REF bit to 1) |
| 9 | VREF_DIV | R/W | 1b |
0b = Sense amplifier reference voltage is VREF (unidirectional mode) 1b = Sense amplifier reference voltage is VREF divided by 2 |
| 8 | LS_REF | R/W | 0b |
0b = VDS_OCP for the low-side MOSFET is measured across SHx to SPx 1b = VDS_OCP for the low-side MOSFET is measured across SHx to SNx |
| 7-6 | CSA_GAIN | R/W | 10b |
00b = 5-V/V shunt amplifier gain 01b = 10-V/V shunt amplifier gain 10b = 20-V/V shunt amplifier gain 11b = 40-V/V shunt amplifier gain |
| 5 | DIS_SEN | R/W | 0b |
0b = Sense overcurrent fault is enabled 1b = Sense overcurrent fault is disabled |
| 4 | CSA_CAL_A | R/W | 0b |
0b = Normal sense amplifier A operation 1b = Short inputs to sense amplifier A for offset calibration |
| 3 | CSA_CAL_B | R/W | 0b |
0b = Normal sense amplifier B operation 1b = Short inputs to sense amplifier B for offset calibration |
| 2 | CSA_CAL_C | R/W | 0b |
0b = Normal sense amplifier C operation 1b = Short inputs to sense amplifier C for offset calibration |
| 1-0 | SEN_LVL | R/W | 11b |
00b = Sense OCP 0.25 V 01b = Sense OCP 0.5 V 10b = Sense OCP 0.75 V 11b = Sense OCP 1 V |