ZHCSIN3A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Three Phase Smart Gate Drivers
- 8.3.2 DVDD Linear Voltage Regulator
- 8.3.3 Pin Diagrams
- 8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
- 8.3.5 Step-Down Buck Regulator
- 8.3.6
Gate Driver Protective Circuits
- 8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
- 8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
- 8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
- 8.3.6.5 Gate Driver Fault (GDF)
- 8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
- 8.3.6.7 Thermal Warning (OTW)
- 8.3.6.8 Thermal Shutdown (OTSD)
- 8.3.6.9 Fault Response Table
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 Status Registers
- 8.6.2
Control Registers
- 8.6.2.1 Driver Control Register (address = 0x02h)
- 8.6.2.2 Gate Drive HS Register (address = 0x03h)
- 8.6.2.3 Gate Drive LS Register (address = 0x04h)
- 8.6.2.4 OCP Control Register (address = 0x05h)
- 8.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
- 8.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Primary Application
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 External MOSFET Support
- 9.2.1.2.2 IDRIVE Configuration
- 9.2.1.2.3 VDS Overcurrent Monitor Configuration
- 9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
- 9.2.1.2.5 Single Supply Power Dissipation
- 9.2.1.2.6 Single Supply Power Dissipation Example
- 9.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
- 9.2.1.3 Application Curves
- 9.2.2 Alternative Application
- 9.2.1
Primary Application
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RTV|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RTV|32
訂購信息
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
- 1 read or write bit, W (bit B15)
- 4 address bits, A (bits B14 through B11)
- 11 data bits, D (bits B11 through B0)
Set the read/write bit (W0, B15) to 0b for a write command. Set the read/write bit (W0, B15) to 1b for a read command.
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The response word is the data currently in the register being accessed.
Table 7. SDI Input Data Word Format
| R/W | ADDRESS | DATA | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
| W0 | A3 | A2 | A1 | A0 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Table 8. SDO Output Data Word Format
| DON'T CARE BITS | DATA | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| B15 | B14 | B13 | B12 | B11 | B10 | B9 | B8 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
| X | X | X | X | X | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Figure 54. SPI Slave Timing Diagram