ZHCSIN3A August 2018 – June 2019 DRV8350 , DRV8350R , DRV8353 , DRV8353R
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Three Phase Smart Gate Drivers
- 8.3.2 DVDD Linear Voltage Regulator
- 8.3.3 Pin Diagrams
- 8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353 and DRV8353R Only)
- 8.3.5 Step-Down Buck Regulator
- 8.3.6
Gate Driver Protective Circuits
- 8.3.6.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
- 8.3.6.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
- 8.3.6.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 8.3.6.4 VSENSE Overcurrent Protection (SEN_OCP)
- 8.3.6.5 Gate Driver Fault (GDF)
- 8.3.6.6 Overcurrent Soft Shutdown (OCP Soft)
- 8.3.6.7 Thermal Warning (OTW)
- 8.3.6.8 Thermal Shutdown (OTSD)
- 8.3.6.9 Fault Response Table
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 Status Registers
- 8.6.2
Control Registers
- 8.6.2.1 Driver Control Register (address = 0x02h)
- 8.6.2.2 Gate Drive HS Register (address = 0x03h)
- 8.6.2.3 Gate Drive LS Register (address = 0x04h)
- 8.6.2.4 OCP Control Register (address = 0x05h)
- 8.6.2.5 CSA Control Register (DRV8353 and DRV8353R Only) (address = 0x06h)
- 8.6.2.6 Driver Configuration Register (DRV8353 and DRV8353R Only) (address = 0x07h)
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Primary Application
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 External MOSFET Support
- 9.2.1.2.2 IDRIVE Configuration
- 9.2.1.2.3 VDS Overcurrent Monitor Configuration
- 9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353 and DRV8353R)
- 9.2.1.2.5 Single Supply Power Dissipation
- 9.2.1.2.6 Single Supply Power Dissipation Example
- 9.2.1.2.7 Buck Regulator Configuration (DRV8350R and DRV8353R)
- 9.2.1.3 Application Curves
- 9.2.2 Alternative Application
- 9.2.1
Primary Application
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
7.6 SPI Timing Requirements
at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| tREADY | SPI ready after enable | VM > UVLO, ENABLE = 3.3 V | 1 | ms | ||
| tCLK | SCLK minimum period | 100 | ns | |||
| tCLKH | SCLK minimum high time | 50 | ns | |||
| tCLKL | SCLK minimum low time | 50 | ns | |||
| tSU_SDI | SDI input data setup time | 20 | ns | |||
| tH_SDI | SDI input data hold time | 30 | ns | |||
| tD_SDO | SDO output data delay time | SCLK high to SDO valid | 30 | ns | ||
| tSU_nSCS | nSCS input setup time | 50 | ns | |||
| tH_nSCS | nSCS input hold time | 50 | ns | |||
| tHI_nSCS | nSCS minimum high time before active low | 400 | ns | |||
| tDIS_nSCS | nSCS disable time | nSCS high to SDO high impedance | 10 | ns | ||
Figure 1. SPI Slave Mode Timing Diagram