7.3.4 Dynamic PDN Analysis
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL), Impedance (Z) and PCB Frequency of Interest (Fpcb).
- LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s power supply and ground reference terminals when viewed from the decoupling capacitor with a “theoretical shorted” applied across the Processor’s supply inputs to ground reference.
- Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb frequency range that limits transient noise drops to no more than 5% of min supply voltage during max transient current events.
- Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar spreading and internal package inductances.
Table 7-3 Recommended PDN Characteristics and EVM Decoupling Capacitors (1)(2)(3)(4)(5)
| PDN Analysis: |
Static |
Dynamic |
EVM Decoupling Capacitor Scheme per Supply(6) |
| Supply |
Max Reff(7)
[mΩ] |
Max Dec.
Cap. LL
[nH] |
Max
Impedance(8)
[mΩ] |
Frequency
of Interest
[MHz] |
100 nF |
220 nF |
470 nF |
1μF |
2.2 μF |
4.7 μF |
10 μF |
22 μF |
| vdd_mpu |
18 |
2 |
57 |
20 |
12 |
2 |
2 |
3 |
1 |
1 |
|
1 |
| vdd_dspeve |
22 |
2.5 |
54 |
20 |
8 |
1 |
1 |
2 |
1 |
1 |
1 |
|
| vdd |
32 |
2 |
87 |
50 |
6 |
1 |
1 |
1 |
1 |
1 |
|
|
| vdd_gpu |
22 |
2.5 |
207 |
50 |
6 |
1 |
1 |
1 |
1 |
1 |
|
|
| vdd_iva |
48 |
2 |
800 |
100 |
5 |
|
1 |
|
|
1 |
|
|
| vdds_ddr1 |
18 |
2.5 |
200 |
100 |
8 |
4 |
|
2 |
|
2 |
|
1 |
| vdds_ddr2 |
18 |
2.5 |
200 |
100 |
8 |
4 |
|
2 |
|
2 |
|
1 |
| cap_vbbldo_dspeve |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vbbldo_gpu |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vbbldo_iva |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vbbldo_mpu |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_core1 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_core2 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_core3 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_core4 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_core5 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_dspeve1 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_dspeve2 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_gpu |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_iva |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_mpu1 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
| cap_vddram_mpu2 |
N/A |
6 |
N/A |
N/A |
|
|
|
1 |
|
|
|
|
- For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
- ESL must be as low as possible and must not exceed 0.5 nH.
- The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency) based on the Recommended Operating Conditions table of the Specifications chapter.
- The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor power balls.
- Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
- Decoupling capacitor (Dcap) scheme optimized for EVM PCB design. Each PCB design could have a different optimal Dcap scheme depending upon stackup, routing, placement and Dcap footprint to via connections.
- Maximum Reff from SMPS to Processor.
- Maximum impedance value at the Frequency of Interest and below.
NOTE
For power IC which can support more than 10 µF close to processor, a bulk capacitor of at least 22 µF is strongly recommended for VDD_MPU power domains.