ZHCSJ46F December 2016 – December 2018 DRA74P , DRA75P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Table 5-32 summarizes the DLL characteristics and assumes testing over recommended operating conditions.
| NAME | DESCRIPTION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| finput | Input clock frequency (EMIF_DLL_FCLK) | 266 | MHz | ||
| tlock | Lock time | 50k | cycles | ||
| trelock | Relock time (a change of the DLL frequency implies that DLL must relock) | 50k | cycles |