ZHCSJ46F December 2016 – December 2018 DRA74P , DRA75P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Table 5-140 presents timing requirements and switching characteristics for MMC1 - SDR104 in receiver and transmitter mode (see Figure 5-93 and Figure 5-94)
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR1041 | fop(clk) | Operating frequency, mmc1_clk | 192 | MHz | |
| SDR1042H | tw(clkH) | Pulse duration, mmc1_clk high | 0.5P-0.185 (1) | ns | |
| SDR1042L | tw(clkL) | Pulse duration, mmc1_clk low | 0.5P-0.185 (1) | ns | |
| SDR1045 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -1.09 | 0.49 | ns |
| SDR1046 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -1.09 | 0.49 | ns |
Figure 5-93 MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
Figure 5-94 MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode