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ZHCSJ46F December 2016 – December 2018 DRA74P , DRA75P

ADVANCE INFORMATION for pre-production products; subject to change without notice.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

ABZ|760
- MPBGAN4A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsj46f_oa

5.10.6.13 QSPI

The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.

General SPI features:

Programmable clock divider
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
4 external chip select signals
Support for 3-, 4- or 6-pin SPI interface
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
Programmable signal polarities
Programmable active clock edge
Software controllable interface allowing for any type of SPI transfer

NOTE

For more information, see the Quad Serial Peripheral Interface section of the Device TRM.

CAUTION

The IO Timings provided in this section are only valid for some QSPI usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.

CAUTION

The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode3).

Table 5-76 and Table 5-77 present timing and switching characteristics for Quad SPI interface.

Table 5-76 Switching Characteristics for QSPI

No	PARAMETER	DESCRIPTION	Mode	MIN	MAX	UNIT
Q1	t_c(SCLK)	Cycle time, sclk	Manual IO Timing Modes, Clock Mode 0	10.41		ns
			Manual IO Timing Modes, Clock Mode 3	13.02		ns
			Bootmode, Clock Mode 3	20.8		ns
Q2	t_w(SCLKL)	Pulse duration, sclk low	All	Y×P-1 ^⁽¹⁾		ns
Q3	t_w(SCLKH)	Pulse duration, sclk high	All	Y×P-1 ^⁽¹⁾		ns
Q4	t_d(CS-SCLK)	Delay time, sclk falling edge to cs active edge, CS3:0	Manual IO Timing Modes	-M×P-1 ^⁽²⁾^⁽³⁾	-M×P+2 ^⁽²⁾^⁽³⁾	ns
Q4	t_d(CS-SCLK)	Delay time, sclk falling edge to cs active edge, CS3:0	Bootmode	-M×P-2.5 ^⁽²⁾^⁽³⁾	-M×P+2.5 ^⁽²⁾^⁽³⁾	ns
Q5	t_d(SCLK-CS)	Delay time, sclk falling edge to cs inactive edge, CS3:0	Manual IO Timing Modes	N×P-1 ^⁽²⁾^⁽³⁾	N×P+2 ^⁽²⁾^⁽³⁾	ns
Q5	t_d(SCLK-CS)	Delay time, sclk falling edge to cs inactive edge, CS3:0	Bootmode	N×P-2.5 ^⁽²⁾^⁽³⁾	N×P+2.5 ^⁽²⁾^⁽³⁾	ns
Q6	t_d(SCLK-D1)	Delay time, sclk falling edge to d[0] transition	Manual IO Timing Modes	-1	2	ns
Q6	t_d(SCLK-D1)	Delay time, sclk falling edge to d[0] transition	Bootmode	-2.5	2.5	ns
Q7	t_ena(CS-D1LZ)	Enable time, cs active edge to d[0] driven (lo-z)	All	-P-3.5	-P+2.5	ns
Q8	t_dis(CS-D1Z)	Disable time, cs active edge to d[0] tri-stated (hi-z)	All	-P-2.5	-P+2.0	ns
Q9	t_d(SCLK-D0)	Delay time, sclk first falling edge to first d[0] transition	Manual IO Timing Modes, PHA=0 Only	-1-P	2-P	ns
Q9	t_d(SCLK-D0)		Bootmode, PHA=0 Only	-2.5-P	2.5-P	ns

The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division factor DCLK_DIV can be found in the Device TRM.
P = SCLK period.
M = QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M = QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.

DRA75P DRA74P SPRS85v_TIMING_QSPI1_01.gif

Figure 5-58 QSPI Read (Clock Mode 3)

DRA75P DRA74P SPRS85v_TIMING_QSPI1_02.gif

Figure 5-59 QSPI Read (Clock Mode 0)

CAUTION

Table 5-77 Timing Requirements for QSPI^⁽²⁾^⁽³⁾

No	PARAMETER	DESCRIPTION	Mode	MIN	UNIT
Q12	t_su(D-RTCLK)	Setup time, d[3:0] valid before falling rtclk edge	Manual IO Timing Modes, Clock Mode 0	2.9	ns
	t_su(D-SCLK)	Setup time, d[3:0] valid before falling sclk edge	Manual IO Timing Modes, Clock Mode 3	5.7	ns
	t_su(D-SCLK)	Setup time, d[3:0] valid before falling sclk edge	Boot Mode, Clock Mode 3	12.3	ns
Q13	t_h(RTCLK-D)	Hold time, d[3:0] valid after falling rtclk edge	Manual IO Timing Mode, Clock Mode 0	-0.1	ns
	t_h(SCLK-D)	Hold time, d[3:0] valid after falling sclk edge	Manual IO Timing Mode, Clock Mode 3	0.1	ns
	t_h(SCLK-D)	Hold time, d[3:0] valid after falling sclk edge	Boot Mode, Clock Mode 3	0.1	ns
Q14	t_su(D-SCLK)	Setup time, final d[3:0] bit valid before final falling sclk edge	Manual IO Timing Mode, Clock Mode 3	5.7-P ^⁽¹⁾	ns
Q14	t_su(D-SCLK)		Boot Mode, Clock Mode 3	12.3-P ^⁽¹⁾	ns
Q15	t_h(SCLK-D)	Hold time, final d[3:0] bit valid after final falling sclk edge	Manual IO Timing Mode, Clock Mode 3	0.1+P ^⁽¹⁾	ns
Q15	t_h(SCLK-D)		Boot Mode, Clock Mode 3	0.1+P ^⁽¹⁾	ns

P = SCLK period.
Clock Modes 1 and 2 are not supported.
The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that launch data on the falling edge in Clock Modes 0 and 3.

DRA75P DRA74P SPRS85v_TIMING_QSPI1_03.gif

Figure 5-60 QSPI Write (Clock Mode 3)

DRA75P DRA74P SPRS85v_TIMING_QSPI1_04.gif

Figure 5-61 QSPI Write (Clock Mode 0)

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information, see the Control Module chapter in the Device TRM.

Manual IO Timings Modes must be used to guarantee some IO timings for QSPI. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-78, Manual Functions Mapping for QSPI for a definition of the Manual modes.

Table 5-78 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-78 Manual Functions Mapping for QSPI

BALL	BALL NAME	QSPI_MODE0_MANUAL1		QSPI_MODE3_MANUAL1		CFG REGISTER	MUXMODE
BALL	BALL NAME	A_DELAY (ps)	G_DELAY (ps)	A_DELAY (ps)	G_DELAY (ps)	CFG REGISTER	1
R3	gpmc_a13	0	0	0	0	CFG_GPMC_A13_IN	qspi1_rtclk
T2	gpmc_a14	2149	1052	0	0	CFG_GPMC_A14_IN	qspi1_d3
U2	gpmc_a15	2121	997	0	0	CFG_GPMC_A15_IN	qspi1_d2
U1	gpmc_a16	2159	1134	0	0	CFG_GPMC_A16_IN	qspi1_d0
U1	gpmc_a16	0	0	0	0	CFG_GPMC_A16_OUT	qspi1_d0
P3	gpmc_a17	2135	1085	0	0	CFG_GPMC_A17_IN	qspi1_d1
R2	gpmc_a18	0	0	151	0	CFG_GPMC_A18_OUT	qspi1_sclk
T7	gpmc_a3	0	0	0	0	CFG_GPMC_A3_OUT	qspi1_cs2
P6	gpmc_a4	0	0	0	0	CFG_GPMC_A4_OUT	qspi1_cs3
P2	gpmc_cs2	0	0	0	0	CFG_GPMC_CS2_OUT	qspi1_cs0
P1	gpmc_cs3	0	0	22	0	CFG_GPMC_CS3_OUT	qspi1_cs1

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

5.10.6.13 QSPI

Table 5-76 Switching Characteristics for QSPI

Table 5-77 Timing Requirements for QSPI(2)(3)

Table 5-78 Manual Functions Mapping for QSPI

Table 5-77 Timing Requirements for QSPI^⁽²⁾^⁽³⁾