ZHCSDE3I February 2015 – January 2025 DP83867CR , DP83867IR
PRODUCTION DATA
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The DP83867 has several internal clocks, including the local reference clock, the Ethernet transmit clock, and the Ethernet receive clock. An external crystal or oscillator provides the stimulus for the local reference clock. The local reference clock acts as the central source for all clocking in the device.
The local reference clock is embedded into the transmit network packet traffic and is recovered from the network packet traffic at the receiver node. The receive clock is recovered from the received Ethernet packet data stream and is locked to the transmit clock in the partner.
Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal clocks through the CLK_OUT pin. By default, the output clock is synchronous to the XI oscillator / crystal input. Through registers, the output clock can be configured to be synchronous to the receive data at the 125MHz data rate or at the divide by 5 rate of 25MHz. It can also be configured to output the line driver transmit clock. When operating in 1000Base-T mode, the output clock can be configured for any of the four transmit or receive channels.
The output clock can be disabled using the CLK_O_DISABLE bit of the I/O Configuration register. It can also be disabled by default using the Clock Out Disable strap. This strap is only available for the PAP devices. For more information, see Section 7.5.1.