ZHCSDE3I February 2015 – January 2025 DP83867CR , DP83867IR
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| BIT | BIT NAME | DEFAULT | DESCRIPTION |
|---|---|---|---|
|
15:12 |
Reserved |
0000,RO |
RESERVED |
|
11:8 |
TXG_GAINSEL_FINE_B |
trim,RW |
Gain control channel B. For details, see bits [3:0] |
|
7:4 |
Reserved |
0000,RO |
RESERVED |
|
3:0 |
TXG_GAINSEL_FINE_A |
trim,RW |
Gain control channel A. Default value is set by trim. Possible values: x0000 = -16% change in gain x0001 = -14% change in gain x1000 = No change in gain x1001 = +2% change in gain x1111 = +14% change in gain |