ZHCSDE3I February 2015 – January 2025 DP83867CR , DP83867IR
PRODUCTION DATA
請參考 PDF 數據表獲取器件具體的封裝圖。
If an external clock source is used, XO can be left floating. For a 1.8V clock source, XI can be tied to the clock source. For a 3.3V or 2.5V clock source, a capacitor divider is recommended as shown in Figure 8-3. For a 3.3V clock source, the CD1 and CD2 capacitors used are recommended to be 27pF. If a 2.5V clock source is used check with the vendor for recommended capacitor loads. The values of CD1 and CD2 shall be adjusted to meet XI Input pin specification defined in Section 6.5.
Figure 8-3 Clock DividerThe CMOS 25MHz oscillator specifications are listed in Table 8-2. Additionally, the maximum oscillator phase noise tolerated by the PHY is shown in Figure 8-4
| PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| Frequency | 25 | MHz | |||
| Frequency Tolerance | Operational Temperature | ±50 | ppm | ||
| Frequency Stability | 1 year aging | ±50 | ppm | ||
| Rise / Fall Time | 20% - 80% | 5 | ns | ||
| Symmetry | Duty Cycle | 40% | 60% | ||
| Jitter RMS | Integration Band: 12kHz to 5MHz | 11 | ps |
Figure 8-4 25MHz Oscillator Phase Noise