Recommend to provide >1-mA
current on the resistor divider ladder to allow faster charging time on the VS
pin filter capacitor.
Appropriate resistor dividers are
needed to bring the high voltage signals within the dynamic range of the ADC.
The resistors in the ladder can be comprised of several resistors in order to
distribute the power dissipation. The portion of the divider below the ADC input
can be made up of parallel resistors to ensure that the ADC input does not fly
to a high voltage when any one resistor becomes open.
Ensure that the voltages on AUX4 >= V_AUX3 >= V_AUX2 >= V_AUX1 >= V_AUX0.
Ensure the input voltage from VS3
and higher to be ≥ 3 V. VS1 to VS2 input can be <3 V, but must be >0 V
with respected to device ground.
Short unused VS pins to VPWR as
shown in Figure 9-7.
Short unused NC pins between 2
and 24 (including 2, 24) to VPWR as shown in Figure 9-8.
The highest VS voltage input and
VPWR voltage should maintain the following relationship for best voltage
measurement accuracy:
VPWR ≥ (1/2 the highest
VS voltage + 2 V)
If the min VPWR is 9 V in
the application, then when VPWR = 9 V, the highest VS voltage input
shall ≤ (9 V -2) x 2 = 14 V
If using MOSFET switches
, ensure that the highest measurement voltage is lower than
(Vmosfet_gate – Vgs_mosfet).