ZHCSTD7A December 2021 – November 2023 BQ79631-Q1
PRODUCTION DATA
The internal power supply circuits have overvoltage, undervoltage, oscillation detection, and/or current limit checks. All these detections are continuously running in the background when the device is in ACTIVE or SLEEP mode. If a failure is detected, the corresponding flags in the FAULT_PWR* registers will be set or in certain failure modes, the device will reset. Table 8-27 summarizes the diagnostics that apply for each power supply and the corresponding action when failure is detected.
| Supply/ Ground Pin | OV Check | UV Check | OSC Check | Current Limit | Pin Open |
|---|---|---|---|---|---|
| LDOIN | |||||
| AVDD | If this fails, set FAULT_PWR1[AVDD_OV] | If this fails, disable DVDD and trigger a digital reset. After soft reset, device sets [AVDDUV_DRST] to indicate a reset is caused by AVDD UV. | If fails, set FAULT_PWR1[AVDD_OSC] | Limit current to EC table current limit specification | |
| DVDD | If this fails, set FAULT_PWR1[DVDD_OV] | If this fails, trigger a digital reset | Limit current to EC table current limit specification | ||
| CVDD | If this fails, set FAULT_PWR1[CVDD_OV] | If this fails, set FAULT_PWR1[CVDD_UV] | Limit current to EC table current limit specification | ||
| TSREF | If this fails, set FAULT_PWR2[TSREF_OV] registers to all 1s. | If this fails, set FAULT_PWR2[TSREF_UV] registers to all 1s. | If fails, set FAULT_PWR2[TSREF_OSC] registers to all 1s. | Limit current to EC table current limit specification | |
| NEG5V | If this fails, set FAULT_PWR2[NEG5V_UV] | ||||
| REFHP/REFHM | If REFHP fails, set FAULT_PWR2[REFH_OSC] | If REFHM opens, set the FAULT_PWR1 [REFHM_OPEN] | |||
| DVSS | If this opens, set the FAULT_PWR1[DVSS_OPEN] | ||||
| CVSS | If this opens, set the FAULT_PWR1[CVSS_OPEN] |
Due to the detection logic implemented, when AVDD OV or UV is detected, the AVDD OSC fault can also be triggered. Similarly, when TSREF OV or UV, the TSREF OSC fault can also be triggered.