ZHCSTD7A December 2021 – November 2023 BQ79631-Q1
PRODUCTION DATA
Each differential VS channel measurement is equipped with a post-ADC LPF. The LPFs have much lower cutoff frequency (fcutoff). There are seven fcutoff options: 6.5 Hz, 13 Hz, 26 Hz, 53 Hz, 111 Hz, 240 Hz, and 600 Hz, configurable through the ADC_CONF1[LPF_VS2:0] setting. Once an fcutoff value is selected and the LPFs are enabled by setting ADC_CTRL1[LPF_VS_EN] = 1, the same fcutoff setting applies to all VS channel measurements.
The digital LPF is implemented as single-pole filter which responds very similarly as an analog RC circuit. This means the Main ADC will be running in continuous mode for the digital LPFs to produce effective filtered results.
The MCU should take into account the digital filter settling time when there is a step change in the input DC voltage level. Equation below gives a typical estimate of digital filter settling time to hit settling accuracy threshold for a step in VS voltage.
Digital Filter Settling Time ~ [ ({log10 (Settling Accuracy Threshold [mV] / Voltage Step in Input Voltage [mV])} / {log10(1 - Filter Coefficient)}) - 1] x 0.192 ms
| Fcutoff (Hz) | 600 | 240 | 111 | 53 | 26 | 13 | 6.5 |
|---|---|---|---|---|---|---|---|
| Filter Coefficient | 0.5 | 0.25 | 0.125 | 0.0625 | 0.03125 | 0.015625 | 0.007813 |
For example: If VS step by 15 mV, and user has to accommodate ~27-ms settling time to within 1 LSB of input step for 26-Hz LPF setting.
When the LPF starts, from disabled to enabled state, it jumps to its first input value and starts the filtering from that point. As compared to starting from 0 V or some mid-level voltage, this implementation allows a fast settling time for Main ADC and LFP is just starting.