ZHCSVT2A April 2022 – April 2024 BQ76922
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fSCL | Clock operating frequency(1) | SCL duty cycle = 50% | 100 | kHz | ||
| tHD:STA | START condition hold time(1) | 4.0 | μs | |||
| tLOW | Low period of the SCL clock(1) | 4.7 | μs | |||
| tHIGH | High period of the SCL clock(1) | 4.0 | μs | |||
| tSU:STA | Setup repeated START(1) | 4.7 | μs | |||
| tHD:DAT | Data hold time (SDA input)(1) | 0 | ns | |||
| tSU:DAT | Data setup time (SDA input)(1) | 250 | ns | |||
| tr | Clock rise time(1) | 10% to 90% | 1000 | ns | ||
| tf | Clock fall time(1) | 90% to 10% | 300 | ns | ||
| tSU:STO | Setup time STOP condition(1) | 4.0 | μs | |||
| tBUF | Bus free time STOP to START(1) | 4.7 | μs | |||
| tRST | I2C bus reset(1) | Bus interface is reset if SCL is detected low for this duration | 1.9 | 2.1 | s | |
| RPULLUP | Pullup resistor(2) | Pullup voltage rail ≤ 5 V | 1.5 | k? | ||