ZHCSVT2A April 2022 – April 2024 BQ76922
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information BQ76922
- 6.5 Supply Current
- 6.6 Digital I/O
- 6.7 LD Pin
- 6.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive
- 6.9 FUSE Pin Functionality
- 6.10 REG18 LDO
- 6.11 REG0 Pre-regulator
- 6.12 REG1 LDO
- 6.13 Voltage References
- 6.14 Coulomb Counter
- 6.15 Coulomb Counter Digital Filter (CC1)
- 6.16 Current Measurement Digital Filter (CC2)
- 6.17 Current Wake Detector
- 6.18 Analog-to-Digital Converter
- 6.19 Cell Balancing
- 6.20 Cell Open Wire Detector
- 6.21 Internal Temperature Sensor
- 6.22 Thermistor Measurement
- 6.23 Internal Oscillators
- 6.24 High-side NFET Drivers
- 6.25 Comparator-Based Protection Subsystem
- 6.26 Timing Requirements – I2C Interface, 100kHz Mode
- 6.27 Timing Requirements – I2C Interface, 400kHz Mode
- 6.28 Timing Requirements – HDQ Interface
- 6.29 Interface Timing Diagrams
- 6.30 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Diagnostics
- 7.4 Device Configuration
- 7.5
Measurement Subsystem
- 7.5.1 Voltage Measurement
- 7.5.2 General Purpose ADCIN Functionality
- 7.5.3 Coulomb Counter and Digital Filters
- 7.5.4 Synchronized Voltage and Current Measurement
- 7.5.5 Internal Temperature Measurement
- 7.5.6 Thermistor Temperature Measurement
- 7.5.7 Factory Trim of Voltage ADC
- 7.5.8 Voltage Calibration (ADC Measurements)
- 7.5.9 Voltage Calibration (COV and CUV Protections)
- 7.5.10 Current Calibration
- 7.5.11 Temperature Calibration
- 7.6 Primary and Secondary Protection Subsystems
- 7.7
Device
Hardware Features
- 7.7.1 Voltage References
- 7.7.2 ADC Multiplexer
- 7.7.3 LDOs
- 7.7.4 Standalone Versus Host Interface
- 7.7.5 Multifunction Pin Controls
- 7.7.6 RST_SHUT Pin Operation
- 7.7.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
- 7.7.8 ALERT Pin Operation
- 7.7.9 Fuse Drive
- 7.7.10 Cell Open Wire
- 7.7.11 Low Frequency Oscillator
- 7.7.12 High Frequency Oscillator
- 7.8 Device Functional Modes
- 7.9 Serial Communications Interface
- 7.10 Cell Balancing
- 8 Application and Implementation
- 9 Power Supply Requirements
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RSN|32
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.4 Startup Timing
At initial power up of the BQ76922 device from a SHUTDOWN state, the device progresses through a sequence of events before entering NORMAL mode operation. These are described below for an example configuration, with approximate timing shown for the cases when [FASTADC] = 0 and [FASTADC] = 1.
| Step | Comment | FASTADC Setting | Time (relative to wakeup event) |
|---|---|---|---|
| Wakeup event | Either the TS2 pin is pulled low, or the LD pin is pulled up, triggering the device to exit SHUTDOWN mode. | 0, 1 | 0 |
| REG1 powered | This was measured with the OTP programmed to autonomously power the REG1 LDO. | 0, 1 | 20 ms |
| INITSTART asserted | This was measured with the OTP programmed to provide the INITSTART bit in the Alarm signal on the ALERT pin. | 0, 1 | 23 ms |
| INITCOMP and ADSCAN asserted | This was measured with the OTP programmed to provide the INITCOMP and ADSCAN bits in the Alarm signal on the ALERT pin. | 0 | 47 ms |
| 1 | 35 ms | ||
| FULLSCAN asserted | This was measured with the OTP programmed to provide the FULLSCAN bit in the Alarm signal on the ALERT pin. | 0 | 97 ms |
| 1 | 62 ms | ||
| FETs enabled | This was measured with the OTP programmed to autonomously enable FETs. | 0 | 278 ms |
| 1 | 278 ms |
Figure 8-6 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP with [FASTADC] = 1, [FET_EN] = 1 for autonomous FET control, setup to use one thermistor, and providing the [INITCOMP] flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN.
Figure 8-6 Startup Sequence Using [FASTADC] = 1, with the [INITCOMP] Flag Displayed on the ALERT Pin
Figure 8-6 shows an example of an oscilloscope plot of a startup sequence with the device configured in OTP with [FASTADC] = 0, [FET_EN] = 1 for autonomous FET control, setup to use one thermistor, and providing the [FULLSCAN] flag on the ALERT pin. The TS2 pin is pulled low to initiate device wakeup from SHUTDOWN.
Figure 8-7 Startup Sequence Using [FASTADC] = 0, with the [FULLSCAN] Flag Displayed on the ALERT Pin