ZHCSVT2A April 2022 – April 2024 BQ76922
PRODUCTION DATA
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| Minimum system operating voltage | 12.5V |
| Cell minimum operating voltage | 2.5V |
| Series cell count | 5 |
| Sense resistor | 1mΩ |
| Number of thermistors | 2 (using TS1 and TS2 pins, both for cells) |
| Charge voltage | 22V |
| Maximum charge current | 3.0A |
| Peak discharge current | 20.0A |
| Configuration settings | programmed in OTP during customer production |
| Protection subsystem configuration | Series FET configuration, device monitors, disables FETs upon fault, recovers autonomously |
| OV protection threshold | 4.30V |
| OV protection delay | 500ms |
| OV protection recovery hysteresis | 100mV |
| UV protection threshold | 2.5V |
| UV protection delay | 20ms |
| UV protection recovery hysteresis | 100mV |
| SCD protection threshold | 80mV (corresponding to a nominal 80A, based on a 1mΩ sense resistor) |
| SCD protection delay | 50μs |
| OCD1 protection threshold | 68mV (corresponding to a nominal 68A, based on a 1mΩ sense resistor) |
| OCD1 protection delay | 10 ms |
| OCD2 protection threshold | 56mV (corresponding to a nominal 56A, based on a 1mΩ sense resistor) |
| OCD2 protection delay | 80ms |
| OCD3 protection threshold | 28mV (corresponding to a nominal 28A, based on a 1mΩ sense resistor) |
| OCD3 protection delay | 160ms |
| OCC protection threshold | 8mV (corresponding to a nominal 8A, based on a 1mΩ sense resistor) |
| OCC protection delay | 160ms |
| OTD protection threshold | 60°C |
| OTD protection delay | 2s |
| OTC protection threshold | 45°C |
| OTC protection delay | 2s |
| UTD protection threshold | –20°C |
| UTD protection delay | 10s |
| UTC protection threshold | 0°C |
| UTC protection delay | 5s |
| Host watchdog timeout protection delay | 5s |
| CFETOFF pin functionality | Use as CFETOFF, polarity = normally high, driven low to disable FET |
| DFETOFF pin functionality | Use as DFETOFF, polarity = normally high, driven low to disable FET |
| ALERT pin functionality | Use as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise |
| REG1 LDO Usage | Use for 3.3V output |
| Cell balancing | Enabled when imbalance exceeds 100mV |