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ZHCSVT2A April 2022 – April 2024 BQ76922

PRODUCTION DATA

封裝選項(xiàng)

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSN|32

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsvt2a_oa

6.24 High-side NFET Drivers

Typical values stated where T_A = 25°C and V_BAT = 18.5 V, min/max values stated where T_A = -40°C to 85°C and V_BAT = 4.7 V to 27.5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{(FETON_HI)}	CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ V_BAT ≤ 27.5 V, V_LD ≤ V_DSG⁽¹⁾	CHG/DSG C_L = 20 nF, charge pump high overdrive setting	10	11	13	V
V_{(FETON_HI_LOBAT)}	CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ V_BAT < 8 V, V_LD ≤ V_DSG⁽¹⁾	CHG/DSG C_L = 20 nF, charge pump high overdrive setting	8	11	13	V
V_{(FETON_LO)}	CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ V_BAT ≤ 27.5 V, V_LD ≤ V_DSG⁽¹⁾	CHG/DSG C_L = 20 nF, charge pump low overdrive setting	4.5	5.7	7	V
V_{(FETON_LO_LOBAT)}	CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ V_BAT < 8 V, V_LD ≤ V_DSG⁽¹⁾	CHG/DSG C_L = 20 nF, charge pump low overdrive setting	3.5	5	7	V
V_{(SRCFOL_FETON)}	DSG on voltage with respect to BAT	CHG/DSG C_L = 20 nF, source follower mode		0		V
V_(CHGFETOFF)	CHG off voltage with respect to BAT	CHG/DSG C_L = 20 nF, steady state value			0.4	V
V_(DSGFETOFF)	DSG off voltage with respect to LD	CHG/DSG C_L = 20 nF, steady state value			0.7	V
t_{(FET_ON)}	CHG and DSG rise time	CHG/DSG C_L = 20 nF, R_GATE = 100 Ω, 0.5 V to 4 V gate-source overdrive, charge pump mode⁽³⁾⁽⁴⁾		21	40	μs
t_(CHGFETOFF)	CHG fall time to BAT	CHG C_L = 20 nF, R_GATE = 100 Ω, 90% to 10% of V_(FETON)⁽⁴⁾		46	65	μs
t_(DSGFETOFF)	DSG fall time to LD	DSG C_L = 20 nF, R_GATE = 100 Ω, 90% to 10% of V_(FETON)⁽⁴⁾		2	20	μs
t_{(CP_START)}	Charge pump start up time⁽²⁾	C_L = 20 nF, C_(CP1) = 470 nF, 10% to 90% of V_(FETON)			100	ms
C_(CP1)	Charge pump capacitor⁽²⁾		100	470	2200	nF

(1) When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that V_LD > V_DSG, the voltage at DSG will rise to ≈ V_LD - 0.7 V

(2) Specified by design

(3) Specified by characterization

(4) R_GATE can be optimized during design and system evaluation for best performance. A larger value may be desired to avoid an overly fast FET turn off, which can result in a large voltage transient due to cell and harness inductance.