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ZHCSMY8B September 2020 – January 2022 BQ769142

PRODUCTION DATA

1 特性
2 應用
3 說明
4 Revision History
5 Device Comparison Table
6 Pin Configuration and Functions
7 Specifications
1. 7.1 Absolute Maximum Ratings
2. 7.2 ESD Ratings
3. 7.3 Recommended Operating Conditions
4. 7.4 Thermal Information BQ769142
5. 7.5 Supply Current
6. 7.6 Digital I/O
7. 7.7 LD Pin
8. 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive
9. 7.9 FUSE Pin Functionality
10. 7.10 REG18 LDO
11. 7.11 REG0 Pre-regulator
12. 7.12 REG1 LDO
13. 7.13 REG2 LDO
14. 7.14 Voltage References
15. 7.15 Coulomb Counter
16. 7.16 Coulomb Counter Digital Filter (CC1)
17. 7.17 Current Measurement Digital Filter (CC2)
18. 7.18 Current Wake Detector
19. 7.19 Analog-to-Digital Converter
20. 7.20 Cell Balancing
21. 7.21 Cell Open Wire Detector
22. 7.22 Internal Temperature Sensor
23. 7.23 Thermistor Measurement
24. 7.24 Internal Oscillators
25. 7.25 High-side NFET Drivers
26. 7.26 Comparator-Based Protection Subsystem
27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
29. 7.29 Timing Requirements - HDQ Interface
30. 7.30 Timing Requirements - SPI Interface
31. 7.31 Interface Timing Diagrams
32. 7.32 Typical Characteristics
8 Device Description
1. 8.1 Overview
2. 8.2 BQ769142 Device Versions
3. 8.3 Functional Block Diagram
4. 8.4 Diagnostics
9 Device Configuration
1. 9.1 Commands and Subcommands
2. 9.2 Configuration Using OTP or Registers
3. 9.3 Device Security
4. 9.4 Scratchpad Memory
10Measurement Subsystem
1. 10.1 Voltage Measurement
2. 10.2 General Purpose ADCIN Functionality
3. 10.3 Coulomb Counter and Digital Filters
4. 10.4 Synchronized Voltage and Current Measurement
5. 10.5 Internal Temperature Measurement
6. 10.6 Thermistor Temperature Measurement
7. 10.7 Factory Trim of Voltage ADC
8. 10.8 Voltage Calibration (ADC Measurements)
9. 10.9 Voltage Calibration (COV and CUV Protections)
10. 10.10 Current Calibration
11. 10.11 Temperature Calibration
11Primary and Secondary Protection Subsystems
1. 11.1 Protections Overview
2. 11.2 Primary Protections
3. 11.3 Secondary Protections
4. 11.4 High-Side NFET Drivers
5. 11.5 Protection FETs Configuration and Control
  1. 11.5.1 FET Configuration
  2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
6. 11.6 Load Detect Functionality
12Device Hardware Features
1. 12.1 Voltage References
2. 12.2 ADC Multiplexer
3. 12.3 LDOs
  1. 12.3.1 Preregulator Control
  2. 12.3.2 REG1 and REG2 LDO Controls
4. 12.4 Standalone Versus Host Interface
5. 12.5 Multifunction Pin Controls
6. 12.6 RST_SHUT Pin Operation
7. 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
8. 12.8 ALERT Pin Operation
9. 12.9 DDSG and DCHG Pin Operation
10. 12.10 Fuse Drive
11. 12.11 Cell Open Wire
12. 12.12 Low Frequency Oscillator
13. 12.13 High Frequency Oscillator
13Device Functional Modes
1. 13.1 Overview
2. 13.2 NORMAL Mode
3. 13.3 SLEEP Mode
4. 13.4 DEEPSLEEP Mode
5. 13.5 SHUTDOWN Mode
6. 13.6 CONFIG_UPDATE Mode
14Serial Communications Interface
1. 14.1 Serial Communications Overview
2. 14.2 I2C Communications
3. 14.3 SPI Communications
  1. 14.3.1 SPI Protocol
4. 14.4 HDQ Communications
15Cell Balancing
1. 15.1 Cell Balancing Overview
16Application and Implementation
1. 16.1 Application Information
2. 16.2 Typical Applications
3. 16.3 Random Cell Connection Support
4. 16.4 Startup Timing
5. 16.5 FET Driver Turn-Off
6. 16.6 Unused Pins
17Power Supply Requirements
18Layout
1. 18.1 Layout Guidelines
2. 18.2 Layout Example
19Device and Documentation Support
1. 19.1 第三方產品免責聲明
2. 19.2 Documentation Support
3. 19.3 支持資源
4. 19.4 Trademarks
5. 19.5 Electrostatic Discharge Caution
6. 19.6 術語表
20Mechanical, Packaging, Orderable Information

封裝選項

機械數據 (封裝 | 引腳)

PFB|48
- MTQF019B

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsmy8b_oa

7.29 Timing Requirements - HDQ Interface

Typical values stated where T_A = 25°C and V_BAT = 59.2 V, min/max values stated where T_A = -40°C to 85°C and V_BAT = 4.7 V to 80 V (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_B	Break Time⁽²⁾		190			μs
t_BR	Break Recovery Time⁽²⁾		40			μs
t_HW1	Host Write 1 Time⁽²⁾	Host drives HDQ	0.5		50	μs
t_HW0	Host Write 0 Time⁽²⁾	Host drives HDQ	86		145	μs
t_CYCH	Cycle Time, Host to device⁽²⁾	Device drives HDQ	190			μs
t_CYCD	Cycle Time, device to Host⁽²⁾	Device drives HDQ	190	205	250	μs
t_DW1	Device Write 1 Time⁽²⁾	Device drives HDQ	32		50	μs
t_DW0	Device Write 0 Time⁽²⁾	Device drives HDQ	80		145	μs
t_RSPS	Device Response Time⁽²⁾ ⁽⁴⁾	Device drives HDQ	190			μs
t_TRND	Host Turn Around Time⁽²⁾	Host drives HDQ after device drives HDQ	210			μs
t_RISE	HDQ Line Rising Time to Logic 1⁽²⁾				1.8	μs
t_RST	HDQ Bus Reset⁽²⁾	Host holds bus low to initiate device interface reset	1.9		2.1	s
R_PULLUP	Pullup Resistor⁽³⁾	Pullup voltage rail ≤ 5 V	1.5			k?

(1) Operation with V_BAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on V_BAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage.

(2) Specified by design

(3) Specified by characterization

(4) Response time will vary depending on the internal device processing