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ZHCSMY8B September 2020 – January 2022 BQ769142

PRODUCTION DATA

1 特性
2 應用
3 說明
4 Revision History
5 Device Comparison Table
6 Pin Configuration and Functions
7 Specifications
1. 7.1 Absolute Maximum Ratings
2. 7.2 ESD Ratings
3. 7.3 Recommended Operating Conditions
4. 7.4 Thermal Information BQ769142
5. 7.5 Supply Current
6. 7.6 Digital I/O
7. 7.7 LD Pin
8. 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive
9. 7.9 FUSE Pin Functionality
10. 7.10 REG18 LDO
11. 7.11 REG0 Pre-regulator
12. 7.12 REG1 LDO
13. 7.13 REG2 LDO
14. 7.14 Voltage References
15. 7.15 Coulomb Counter
16. 7.16 Coulomb Counter Digital Filter (CC1)
17. 7.17 Current Measurement Digital Filter (CC2)
18. 7.18 Current Wake Detector
19. 7.19 Analog-to-Digital Converter
20. 7.20 Cell Balancing
21. 7.21 Cell Open Wire Detector
22. 7.22 Internal Temperature Sensor
23. 7.23 Thermistor Measurement
24. 7.24 Internal Oscillators
25. 7.25 High-side NFET Drivers
26. 7.26 Comparator-Based Protection Subsystem
27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
29. 7.29 Timing Requirements - HDQ Interface
30. 7.30 Timing Requirements - SPI Interface
31. 7.31 Interface Timing Diagrams
32. 7.32 Typical Characteristics
8 Device Description
1. 8.1 Overview
2. 8.2 BQ769142 Device Versions
3. 8.3 Functional Block Diagram
4. 8.4 Diagnostics
9 Device Configuration
1. 9.1 Commands and Subcommands
2. 9.2 Configuration Using OTP or Registers
3. 9.3 Device Security
4. 9.4 Scratchpad Memory
10Measurement Subsystem
1. 10.1 Voltage Measurement
2. 10.2 General Purpose ADCIN Functionality
3. 10.3 Coulomb Counter and Digital Filters
4. 10.4 Synchronized Voltage and Current Measurement
5. 10.5 Internal Temperature Measurement
6. 10.6 Thermistor Temperature Measurement
7. 10.7 Factory Trim of Voltage ADC
8. 10.8 Voltage Calibration (ADC Measurements)
9. 10.9 Voltage Calibration (COV and CUV Protections)
10. 10.10 Current Calibration
11. 10.11 Temperature Calibration
11Primary and Secondary Protection Subsystems
1. 11.1 Protections Overview
2. 11.2 Primary Protections
3. 11.3 Secondary Protections
4. 11.4 High-Side NFET Drivers
5. 11.5 Protection FETs Configuration and Control
  1. 11.5.1 FET Configuration
  2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
6. 11.6 Load Detect Functionality
12Device Hardware Features
1. 12.1 Voltage References
2. 12.2 ADC Multiplexer
3. 12.3 LDOs
  1. 12.3.1 Preregulator Control
  2. 12.3.2 REG1 and REG2 LDO Controls
4. 12.4 Standalone Versus Host Interface
5. 12.5 Multifunction Pin Controls
6. 12.6 RST_SHUT Pin Operation
7. 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
8. 12.8 ALERT Pin Operation
9. 12.9 DDSG and DCHG Pin Operation
10. 12.10 Fuse Drive
11. 12.11 Cell Open Wire
12. 12.12 Low Frequency Oscillator
13. 12.13 High Frequency Oscillator
13Device Functional Modes
1. 13.1 Overview
2. 13.2 NORMAL Mode
3. 13.3 SLEEP Mode
4. 13.4 DEEPSLEEP Mode
5. 13.5 SHUTDOWN Mode
6. 13.6 CONFIG_UPDATE Mode
14Serial Communications Interface
1. 14.1 Serial Communications Overview
2. 14.2 I2C Communications
3. 14.3 SPI Communications
  1. 14.3.1 SPI Protocol
4. 14.4 HDQ Communications
15Cell Balancing
1. 15.1 Cell Balancing Overview
16Application and Implementation
1. 16.1 Application Information
2. 16.2 Typical Applications
3. 16.3 Random Cell Connection Support
4. 16.4 Startup Timing
5. 16.5 FET Driver Turn-Off
6. 16.6 Unused Pins
17Power Supply Requirements
18Layout
1. 18.1 Layout Guidelines
2. 18.2 Layout Example
19Device and Documentation Support
1. 19.1 第三方產品免責聲明
2. 19.2 Documentation Support
3. 19.3 支持資源
4. 19.4 Trademarks
5. 19.5 Electrostatic Discharge Caution
6. 19.6 術語表
20Mechanical, Packaging, Orderable Information

封裝選項

機械數據 (封裝 | 引腳)

PFB|48
- MTQF019B

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsmy8b_oa

16.2.1 Design Requirements (Example)

Table 16-1 BQ769142 Design Requirements

DESIGN PARAMETER	EXAMPLE VALUE
Minimum system operating voltage	35 V
Cell minimum operating voltage	2.5 V
Series cell count	14
Sense resistor	1 mΩ
Number of thermistors	3 (using TS1, TS2, and TS3 pins, all for cells)
Charge voltage	60 V
Maximum charge current	8.0 A
Peak discharge current	20.0 A
Configuration settings	Programmed in OTP during customer production
Protection subsystem configuration	Series FET configuration, device monitors, disables FETs upon fault, recovers autonomously
OV protection threshold	4.35 V
OV protection delay	500 ms
OV protection recovery hysteresis	100 mV
UV protection threshold	2.5 V
UV protection delay	20 ms
UV protection recovery hysteresis	100 mV
SCD protection threshold	80 mV (corresponding to a nominal 80 A, based on a 1-mΩ sense resistor)
SCD protection delay	50 μs
OCD1 protection threshold	68 mV (corresponding to a nominal 68 A, based on a 1-mΩ sense resistor)
OCD1 protection delay	10 ms
OCD2 protection threshold	56 mV (corresponding to a nominal 56 A, based on a 1-mΩ sense resistor)
OCD2 protection delay	80 ms
OCD3 protection threshold	28 mV (corresponding to a nominal 28 A, based on a 1-mΩ sense resistor)
OCD3 protection delay	160 ms
OCC protection threshold	8 mV (corresponding to a nominal 8 A, based on a 1-mΩ sense resistor)
OCC protection delay	160 ms
OTD protection threshold	60°C
OTD protection delay	2 s
OTC protection threshold	45°C
OTC protection delay	2 s
UTD protection threshold	–20°C
UTD protection delay	10 s
UTC protection threshold	0°C
UTC protection delay	5 s
Host watchdog timeout protection delay	5 s
CFETOFF pin functionality	Use as CFETOFF, polarity = normally high, driven low to disable FET
DFETOFF pin functionality	Use as DFETOFF, polarity = normally high, driven low to disable FET
ALERT pin functionality	Use as ALERT interrupt pin, polarity = driven low when active, hi-Z otherwise
REG1 LDO Usage	Use for 3.3-V output
Cell balancing	Enabled when imbalance exceeds 100 mV