ZHCSMY8B September 2020 – January 2022 BQ769142
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fSCL | Clock operating frequency(2) | SCL duty cycle = 50% | 400 | kHz | ||
| tHD:STA | START condition hold time(2) | 0.6 | μs | |||
| tLOW | Low period of the SCL clock(2) | 1.3 | μs | |||
| tHIGH | High period of the SCL clock(2) | 600 | ns | |||
| tSU:STA | Setup repeated START(2) | 600 | ns | |||
| tHD:DAT | Data hold time (SDA input)(2) | 0 | ns | |||
| tSU:DAT | Data setup time (SDA input)(2) | 100 | ns | |||
| tr | Clock rise time(2) | 10% to 90% | 300 | ns | ||
| tf | Clock fall time(2) | 90% to 10% | 300 | ns | ||
| tSU:STO | Setup time STOP condition(2) | 0.6 | μs | |||
| tBUF | Bus free time STOP to START(2) | 1.3 | μs | |||
| tRST | I2C bus reset(2) | Bus interface is reset if SCL is detected low for this duration | 1.9 | 2.1 | s | |
| RPULLUP | Pullup resistor(3) | Pullup voltage rail ≤ 5 V | 1.5 | k? | ||