国产精品高清一区二区三区,美女极品粉嫩美鮑20P图,91亚洲精品福利在线播放

ZHCSMY8B September 2020 – January 2022 BQ769142

PRODUCTION DATA

1 特性
2 應(yīng)用
3 說(shuō)明
4 Revision History
5 Device Comparison Table
6 Pin Configuration and Functions
7 Specifications
1. 7.1 Absolute Maximum Ratings
2. 7.2 ESD Ratings
3. 7.3 Recommended Operating Conditions
4. 7.4 Thermal Information BQ769142
5. 7.5 Supply Current
6. 7.6 Digital I/O
7. 7.7 LD Pin
8. 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive
9. 7.9 FUSE Pin Functionality
10. 7.10 REG18 LDO
11. 7.11 REG0 Pre-regulator
12. 7.12 REG1 LDO
13. 7.13 REG2 LDO
14. 7.14 Voltage References
15. 7.15 Coulomb Counter
16. 7.16 Coulomb Counter Digital Filter (CC1)
17. 7.17 Current Measurement Digital Filter (CC2)
18. 7.18 Current Wake Detector
19. 7.19 Analog-to-Digital Converter
20. 7.20 Cell Balancing
21. 7.21 Cell Open Wire Detector
22. 7.22 Internal Temperature Sensor
23. 7.23 Thermistor Measurement
24. 7.24 Internal Oscillators
25. 7.25 High-side NFET Drivers
26. 7.26 Comparator-Based Protection Subsystem
27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
29. 7.29 Timing Requirements - HDQ Interface
30. 7.30 Timing Requirements - SPI Interface
31. 7.31 Interface Timing Diagrams
32. 7.32 Typical Characteristics
8 Device Description
1. 8.1 Overview
2. 8.2 BQ769142 Device Versions
3. 8.3 Functional Block Diagram
4. 8.4 Diagnostics
9 Device Configuration
1. 9.1 Commands and Subcommands
2. 9.2 Configuration Using OTP or Registers
3. 9.3 Device Security
4. 9.4 Scratchpad Memory
10Measurement Subsystem
1. 10.1 Voltage Measurement
2. 10.2 General Purpose ADCIN Functionality
3. 10.3 Coulomb Counter and Digital Filters
4. 10.4 Synchronized Voltage and Current Measurement
5. 10.5 Internal Temperature Measurement
6. 10.6 Thermistor Temperature Measurement
7. 10.7 Factory Trim of Voltage ADC
8. 10.8 Voltage Calibration (ADC Measurements)
9. 10.9 Voltage Calibration (COV and CUV Protections)
10. 10.10 Current Calibration
11. 10.11 Temperature Calibration
11Primary and Secondary Protection Subsystems
1. 11.1 Protections Overview
2. 11.2 Primary Protections
3. 11.3 Secondary Protections
4. 11.4 High-Side NFET Drivers
5. 11.5 Protection FETs Configuration and Control
  1. 11.5.1 FET Configuration
  2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
6. 11.6 Load Detect Functionality
12Device Hardware Features
1. 12.1 Voltage References
2. 12.2 ADC Multiplexer
3. 12.3 LDOs
  1. 12.3.1 Preregulator Control
  2. 12.3.2 REG1 and REG2 LDO Controls
4. 12.4 Standalone Versus Host Interface
5. 12.5 Multifunction Pin Controls
6. 12.6 RST_SHUT Pin Operation
7. 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
8. 12.8 ALERT Pin Operation
9. 12.9 DDSG and DCHG Pin Operation
10. 12.10 Fuse Drive
11. 12.11 Cell Open Wire
12. 12.12 Low Frequency Oscillator
13. 12.13 High Frequency Oscillator
13Device Functional Modes
1. 13.1 Overview
2. 13.2 NORMAL Mode
3. 13.3 SLEEP Mode
4. 13.4 DEEPSLEEP Mode
5. 13.5 SHUTDOWN Mode
6. 13.6 CONFIG_UPDATE Mode
14Serial Communications Interface
1. 14.1 Serial Communications Overview
2. 14.2 I2C Communications
3. 14.3 SPI Communications
  1. 14.3.1 SPI Protocol
4. 14.4 HDQ Communications
15Cell Balancing
1. 15.1 Cell Balancing Overview
16Application and Implementation
1. 16.1 Application Information
2. 16.2 Typical Applications
3. 16.3 Random Cell Connection Support
4. 16.4 Startup Timing
5. 16.5 FET Driver Turn-Off
6. 16.6 Unused Pins
17Power Supply Requirements
18Layout
1. 18.1 Layout Guidelines
2. 18.2 Layout Example
19Device and Documentation Support
1. 19.1 第三方產(chǎn)品免責(zé)聲明
2. 19.2 Documentation Support
3. 19.3 支持資源
4. 19.4 Trademarks
5. 19.5 Electrostatic Discharge Caution
6. 19.6 術(shù)語(yǔ)表
20Mechanical, Packaging, Orderable Information

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PFB|48
- MTQF019B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

zhcsmy8b_oa

7.19 Analog-to-Digital Converter

Typical values stated where T_A = 25°C and V_BAT = 59.2 V, min/max values stated where T_A = -40°C to 85°C and V_BAT = 4.7 V to 80 V (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{(ADC_IN_CELLS)}	Input voltage range (differential cell input mode)⁽⁵⁾	Internal reference (Vref = V_REF1)	–0.2		5.5	V
V_{(ADC_IN)}	Input voltage range (ADCIN measurement mode)⁽⁶⁾	Internal reference (Vref = V_REF1), applicable to ADCIN measurements using the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins	–0.2		V_REG18	V
V_{(ADC_IN_TS)}	Input voltage range (external thermistor measurement mode)⁽⁷⁾	Regulator reference (Vref = V_REG18), applicable to external thermistor measurements using the TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, and DDSG pins	–0.2		V_REG18	V
V_{(ADC_IN_DIV)}	Input voltage range (divider measurement mode)⁽⁸⁾	Internal reference (Vref = V_REF1), applicable to divider measurements using the VC14, PACK, and LD pins relative to VSS.	–0.2		80	V
B_{(ADC_INL)}	Integral nonlinearity (when using V_REF1and differential cell voltage measurement mode at VC14 - VC13A)⁽⁴⁾	16-bit, best fit over -0.1 V to 5.5 V	–6.6		6.6	LSB⁽⁵⁾
B_{(ADC_INL)}		16-bit, best fit over -0.2 V to 0.2 V	–4		4	LSB⁽⁵⁾
B_{(ADC_DNL)}	Differential nonlinearity	16-bit, no missing codes, using differential cell voltage measurement at VC14-VC13A		±0.12		LSB⁽⁵⁾
B_{(ADC_OFF_CELL)}	Differential cell offset error	16-bit, uncalibrated, using VC14 - VC13A	–2.75		3.5	LSB⁽⁵⁾
B_{(ADC_OFF)}	ADCIN offset error	16-bit, uncalibrated, using ADCIN mode on TS1 pin		0.53		LSB⁽⁶⁾
B_{(ADC_OFF_DIV)}	Divider offset error	16-bit, uncalibrated, using divider mode on PACK pin		0.17		LSB⁽⁸⁾
B_{(ADC_OFF_DRIFT_CELL)}	Differential cell offset error drift⁽⁴⁾	Offset error measured 16-bit, post calibration, using VC14 - VC13A. Drift measured as change in offset over operating temperature range as compared to offset at 30°C.		0.004	0.07	LSB/°C⁽⁵⁾
B_{(ADC_GAIN)}	Gain	Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC14-VC13A, uncalibrated.	5385	5406	5427	LSB/V⁽⁵⁾
B_{(ADC_GAIN_DRIFT)}	Gain drift⁽⁴⁾	Gain measured 16-bit, over ideal input voltage range, differential cell input mode on VC14-VC13A, uncalibrated. Drift value measured as change in gain over operating temperature range, compared to gain at 30°C.	-0.25	0.025	0.25	LSB/V/°C⁽⁵⁾
R_{(ADC_IN_CELL)}	Effective input resistance⁽³⁾	Differential cell input mode on VC14-VC13A⁽⁹⁾	2.1			MΩ
R_{(ADC_IN_LD)}	Effective input resistance	Divider measurement on LD pin (only active while the LD pin is being measured)		2		MΩ
R_{(ADC_IN_DIV)}	Effective input resistance	Divider measurement on VC14 and PACK pins (only active while the pin is being measured)		600		kΩ
B_{(ADC_RES)}	Code stability⁽²⁾ ⁽⁴⁾	Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0	13.5	15		bits
B_{(ADC_RES_FAST)}	Code stability in fast mode⁽²⁾	Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1		14		bits
t_{(ADC_CONV)}	Conversion-time	Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 0		2.93		ms
t_{(ADC_CONV_FAST)}	Conversion-time in fast mode	Single conversion, in NORMAL mode, Settings:Configuration:Power Config[FASTADC] = 1		1.46		ms

(1) Operation with V_BAT up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in 5.5 V or 11 V mode), the maximum voltage on V_BAT should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed their maximum specified voltage.

(2) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.

(3) Specified by design

(4) Specified by characterization

(5) The 16-bit LSB size of the differential cell voltage measurement is given by 1 LSB = 5 x V_REF1 / 2^N-1 ≈ 5 x 1.212 V / 2¹⁵ = 185 μV

(6) The 16-bit LSB size of the ADCIN voltage measurement is given by 1 LSB = 5 / 3 x V_REF1 / 2^N-1 ≈ 5 / 3 x 1.212 V / 2¹⁵ = 62 μV

(7) The LSB size of the external thermistor voltage measurement when reported in 32-bit format is given by 1 LSB = 5 / 3 x V_REG18 / 2^N-1 ≈ 5 / 3 x 1.8 V / 2²³ = 358 nV

(8) The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 425 / 3 x V_REF1 / 2^N-1 ≈ 425 / 3 x 1.212 / 2¹⁵ = 5.24 mV

(9) Average effective differential input resistance with device operating in NORMAL mode, cell balancing disabled, three or more thermistors in use, and a 5 V differential voltage applied.