ZHCSPA6F September 2006 – January 2022
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Communication
- 7.5.2 Initialization
- 7.5.3 ROM Commands
- 7.5.4 Memory/Status Function Commands
- 7.5.5 READ MEMORY Commands
- 7.5.6 WRITE MEMORY Command
- 7.5.7 READ STATUS Command
- 7.5.8 WRITE STATUS Command
- 7.5.9 PROGRAM PROFILE Byte
- 7.5.10 SDQ Signaling
- 7.5.11 RESET and PRESENCE PULSE
- 7.5.12 WRITE Bit
- 7.5.13 READ Bit
- 7.5.14 PROGRAM PULSE
- 7.5.15 IDLE
- 7.5.16 CRC Generation
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
7.5.16 CRC Generation
The BQ2022A has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the BQ2022A to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 +1.
Under certain conditions, the BQ2022A also generates an 8-bit CRC value using the same polynomial function just shown and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the BQ2022A. The BQ2022A computes an 8-bit CRC for the command, address, and data bytes received for the WRITE MEMORY and the WRITE STATUS commands and then outputs this value to the bus master to confirm proper transfer. Similarly, the BQ2022A computes an 8-bit CRC for the command and address bytes received from the bus master for the READ MEMORY, READ STATUS, and READ DATA/ GENERATE 8-BIT CRC commands to confirm that these bytes have been received correctly. The CRC generator on the BQ2022A is also used to provide verification of error-free data transfer as each page of data from the 1024-bit EPROM is sent to the bus master during a READ DATA/GENERATE 8-BIT CRC command, and for the eight bytes of information in the status memory field.
In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function previously given and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the BQ2022A (for ROM reads) or the 8-bit CRC value computed within the BQ2022A. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. No circuitry on the BQ2022A prevents a command sequence from proceeding if the CRC stored in or calculated by the BQ2022A does not match the value generated by the bus master. Proper use of the CRC can result in a communication channel with a high level of integrity.
Figure 7-13 8-Bit CRC Generator Circuit (X8 + X5 + X4 + 1)