ZHCSPA6F September 2006 – January 2022
PRODUCTION DATA
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or to begin the start frame for a bit read. Figure 7-9 shows the initialization timing, whereas Figure 7-10 and Figure 7-11 show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit is initiated, either the host continues controlling the bus during a WRITE, or the BQ2022A responds during a READ.