ZHCSPA6F September 2006 – January 2022
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1 Serial Communication
- 7.5.2 Initialization
- 7.5.3 ROM Commands
- 7.5.4 Memory/Status Function Commands
- 7.5.5 READ MEMORY Commands
- 7.5.6 WRITE MEMORY Command
- 7.5.7 READ STATUS Command
- 7.5.8 WRITE STATUS Command
- 7.5.9 PROGRAM PROFILE Byte
- 7.5.10 SDQ Signaling
- 7.5.11 RESET and PRESENCE PULSE
- 7.5.12 WRITE Bit
- 7.5.13 READ Bit
- 7.5.14 PROGRAM PULSE
- 7.5.15 IDLE
- 7.5.16 CRC Generation
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.5.11 RESET and PRESENCE PULSE
If the DATA bus is driven low for more than 120 μs, the BQ2022A may be reset. Figure 7-9 shows that if the DATA bus is driven low for more than 480 μs, the BQ2022A resets and indicates that it is ready by responding with a PRESENCE PULSE.
Figure 7-9 Reset Timing Diagram