The AMC131M03 device registers must be initialized to deliver proper measurement data on all relevant analog input channels. This initialization process is followed at every start of the metrology application as well as each time the metrology calibration procedure is run.

Figure 3-1 Energy Metrology Initialization Sequence in TIDA-010244 Firmware

The SPI module of the MSPM0+ MCU is configured as a controller device that uses 4-wire mode (the four chip-select signals CS0, CS1, CS2, and CS3 are automatically asserted high and low by the SPI hardware module). After the SPI module is set up, all interrupts are disabled and a reset pulse on the SYNC_RESET line is sent from the MSPM0+ MCU. Interrupts are then re-enabled and the MSPM0+ MCU sends SPI write commands to the ADCs (first to AMC131M03 for Phase A, then the AMC131M03 for Phase B, then AMC131M03 for Phase C, and finally to AMC131M03 for Neutral) to configure the registers:

• MODE register settings: 16-bit CCITT CRC used, 24-bit length for each word in the AMC31M03 data packet, the DRDY signal is asserted on the most lagging enabled channel, DRDY is asserted high when the conversion value is not available, DRDY is asserted low when the conversion values are ready.
• GAINx register settings: PGA gain = 1 used for all three channels, measuring the line-to-neutral voltage on each AMC device
• GAINy register settings: PGA gain = 32 is used for all four current measurement channels (SHUNT channels)
• CHx_CNG register settings (where x is the channel number)
  • 3-phase mode: All seven ADC channel inputs connected to external ADC pins and the channel phase delay set to 0 for each channel (the software phase compensation in the SDK Middleware is used instead of AMC131M03 hardware phase compensation).
• CLOCK register settings: 1024 OSR, all channels enabled, and high-resolution modulator power mode

The MSPM0+ MCU is configured at start-up to generate a port interrupt whenever a falling edge occurs on any of the four DRDY pins, which indicate that new measurement samples are available.

The ADC modulator clock is derived from the clock fed to the CLKIN pin which gets internally divided by two, to generate the ADC modulator clock. The sampling frequency of the ADC is therefore defined as shown in Equation 3.

where

• ?_S is the sampling rate
• ?_M is the modulator clock frequency
• ?_CLKIN is the clock fed to the AMC131M03 CLKIN pin
• OSR is the selected oversampling ratio

In this design, the M0_CLKOUT signal of the MSPM0+ MCU has a frequency of 8.192MHz. The oversampling ratio is selected to be 1024 with the appropriate register setting. As a result, the ADC modulator clock for all four ADCs is set to 4.096MHz and the sample rate is set to 4000 samples per second.

For a 3-phase system where each line-to-neutral voltage is measured, at least three AMC devices are necessary to independently measure three voltages and three currents and isolate between any two phases. In this design, the following ADC channel mappings are used in software for the 3-phase configuration:

• AIN0P and AIN0N of AMC131M03 (U4) → Current I1 (Phase A Current)
• AIN1P and AIN1N of AMC131M03 (U4) → Voltage V1 (Phase A Line-to-Neutral Voltage)
• AIN0P and AIN0N of AMC131M03 (U5) → Current I2 (Phase B Current)
• AIN1P and AIN1N of AMC131M03 (U5) → Voltage V2 (Phase B Line-to-Neutral Voltage)
• AIN0P and AIN0N of AMC131M03 (U6) → Current I3 (Phase C Current)
• AIN1P and AIN1N of AMC131M03 (U6) → Voltage V3 (Phase C Line-to-Neutral Voltage)
• AIN0P and AIN0N of AMC131M03 (U7) → Current N (Neutral Current)