TIDUF27A February 2025 – March 2025 AMC131M03 , MSPM0G1507
This reference design comes with three different options to provide the necessary clock input at the LMK1C1104 to drive the four identical in-phase clock signals CLKIN1 through CLKIN4, making sure all ADCs run and collect data samples synchronized to each other. Both BAW and XTAL configurations were successfully tested, while the PWM option was not tested.
The MSPM0G3507 MCU is configured to have the CPU clock (MCLK) set at 79.87MHz and the M0_CLKOUT clock signal to all AMC131M03 devices is set to 8.192MHz. The external 16.384MHz or 32.768MHz XTAL, which is feeding the PLL module and is being multiplied and divided with specific factors, generates an MCLK frequency (the CPU clock speed) of 79.87MHz. An internal 32.768kHz LFOSC is used as the clock source for the auxiliary RTC clock (RTCCLK) of the device.