From sections 2 and
3,
any variation between ZOUT of the individual LDOs degrades the overall
noise performance predicted by equation 3. The following design practices help equalize
the effective resistance (“R”) seen at each output of the regulator in a parallel
LDO architecture.
- Common input voltage – Feed all
regulators from the same input voltage source so that each device experiences
the same junction temperature and input voltage.
- Matched output capacitors – Use
identical, tight?tolerance capacitors (both value and ESR) on every LDO to keep
the capacitive component of ZOUT consistent.
- Matched ballast resistors – Select
discrete ballast resistors with the same nominal value and low tolerance
(≤?1?%).
- Remote sensing – Connect the
remote?sense pin of the LDO directly to the VOUT pad of the ballast
resistor as a kelvin sense trace to eliminate lead?wire and trace resistance
between VOUT and RB.
- PDN impedance matching – Verify
that the power?distribution network between each ballast resistor and the load,
as well as the return path from the load to the RTN pin of the LDO, has matched
impedance for every regulator.
- Common reference node – Tie the
reference pins of all LDOs together so that the pins share the same reference
voltage.
- Prefer unity?gain architecture –
When possible, select an LDO that operates in unity?gain mode (no external
feedback divider), eliminating one source of mismatch.
- Matched feedback network (if
required) – If the device does not support unity gain, use a feedback
resistor network with identical, low?tolerance parts for each regulator to set
the output voltage.
By applying these eight design
practices, the output impedances of the parallel LDOs become closely matched,
allowing the system to achieve the noise reduction indicated by equation 3.