2 Noise Analysis of Parallel LDOs Using Ballast Resistors

As described in reference [1], parallel LDOs using ballast resistors can be redrawn as shown in the schematic in Figure 2-1, and the V_LOAD formula is provided in equation 1.

Figure 2-1 Equivalent Model for n Parallel LDOs Using Ballast Resistors

Assume a parallel network in which no LDO regulates another LDO, and each feedback loop of the regulator operates independently of the others. Let Z_OUTn denote the output impedance of the n^th LDO in the parallel array. Since the noise analysis is performed under steady?state conditions, the load current I_LOAD contains no AC component; consequently, the load current is constant (for example, the frequency content is zero). Equation 1 can therefore be simplified by applying these assumptions.

1. Set R_Bn = Z_OUTn + R_B = "R"
2. Replace V_OUT1, V_OUT2,…, V_OUTn with noise source e_n
3. Set V_E1 = V_E2 = … = V_En = 0V
4. Set I_LOAD = 0

Using these assumptions, rewrite equation 1 as equations 2 and 3.

The output noise of the parallel LDOs is reduced by the square root of the number of LDOs in parallel. Fundamentally, these assumptions imply that all paralleled LDOs exhibit identical intrinsic noise (because the same LDO IC is used), operate at the same temperature, generate zero or negligible error?voltage, use the same ballast resistors with low tolerance (< 1%), and are closely matched in output impedance (Z_OUT).