STDA017 November 2025 TPS7A33 , TPS7A4501-SP , TPS7A47 , TPS7A47-Q1 , TPS7A4701-EP , TPS7A52 , TPS7A52-Q1 , TPS7A53 , TPS7A53-Q1 , TPS7A53A-Q1 , TPS7A53B , TPS7A54 , TPS7A54-Q1 , TPS7A57 , TPS7A8300 , TPS7A83A , TPS7A84 , TPS7A84A , TPS7A85A , TPS7A90 , TPS7A91 , TPS7A92 , TPS7A94 , TPS7A96 , TPS7B7702-Q1 , TPS7H1111-SEP , TPS7H1111-SP
Other parallel LDO architectures configure one LDO as the primary and the remaining LDOs as the secondary. The primary LDO controls the secondary LDOs through an additional feedback loop. The LDOs do not operate independently from each other, unlike with the ballast resistor technique. For these architectures the preceding analysis is no longer valid and the system noise does not reduce by the √n. These external components can potentially result in an increase in noise, as the feedback loops are typically connected to the unfiltered feedback pin. If the external components carry significant noise, then these components can potentially cause the parallel LDO system to become noisier as well.