SPRZ536B September 2022 – July 2024 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VH-Q1 , TDA4VP-Q1 , TDA4VPE-Q1
C71x: DMA Accesses to L1D SRAM May Stall Indefinitely in the Presence Cache Mode Change or Global Writeback in Specific Conditions
DMA reads or writes to L1D SRAM may stall indefinitely. These transactions are required to sensitize this condition:
These transactions do not need to be to the same address, but #2 and #3 have to be in flight when #1 is in progress. In this case, the DMAs stall indefinitely even after the cache mode change or global Writeback finishes.
Avoid doing DMAs to buffers mapped to L1D SRAM.