SNAU309 October 2025 LMK3H2108
The clock output pairs of the LMK3H2108 are routed via 50Ω single-ended traces to SMA ports (OUT[7:0]_P/ OUT[7:0]_N). These outputs have series resistor (0Ω populated) options. The default output configuration for the LMK3H2108EVM is DC-coupled LP-HCSL for all outputs.. Each of these outputs can be configured for AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS output formats.
For 1.2V LVCMOS outputs, the logic high level is set by setting the OUTx_CMOS_1P2V_EN bit of the output channel to a '1'. When this bit is a 0, the logic high level of LVCMOS outputs is determined by the voltage on the VDDO supply for the output.