A solid-state relay (SSR) uses a semiconductor FET to build high-voltage ability switches with an isolation barrier. Compared with conventional electromechanical relays, SSRs offer a number of distinct advantages.

• High reliability: With no moving contacts, SSRs are free from wear, arcing, and contact?bounce. The rated life of an SSR is typically 10–100?times greater than that of an electromechanical relay, and SSRs are immune to vibration, shock, dust, and humidity, and can operate in wide temperature ranges.
• Fast switching: Compared to mechanical relays switching in several milliseconds and exhibiting bounce, an SSR offers a microsecond-range switching-time and bounce-free operation that enables cleaner voltage on measurement and quicker fault detection.
• Predictable electrical parameters: The on?state resistance and leakage current of an SSR are tightly specified and remain stable throughout a lifetime, unlike the variable contact resistance and uncontrolled leakage of mechanical relays.
• Simple circuit: An SSR can be driven directly from a logic?level signal; an SSR does not require a dedicated driver or a separate power supply for coil excitation, reducing component count and design complexity.
• Compact size: SSRs integrate capacitive isolation within a small package, eliminating the bulky coil, driver, and auxiliary power components that are typical of electromechanical relays, and thereby, saving PCB area.

These benefits directly address the high?cycle, safety?critical requirements of insulation monitoring functions in onboard chargers, so SSRs are the preferred replacement for mechanical relays. Table 3-1 contains the side-by-side comparison of SSRs against traditional options.

The TPSI2140?Q1 is a single?channel, high?voltage solid?state switch from Texas Instruments that integrates MOSFET power devices with an isolated gate?drive interface. The diagram in Figure 3-1 shows the block architecture of the TPSI2140?Q1 device. The device provides the switching capability of one?200V ON/OFF switch and can tolerate an avalanche current of 1mA for up to 60?seconds, enabling high?potential (Hi?Pot) testing. The device is appropriate for implementation in both dual?switch and active single?switch architecture.

Figure 3-1 Unidirectional SSR TPSI2140?Q1 Block Diagram

The TPSI2072?Q1 is a dual?channel, high?voltage, solid?state switch from Texas Instruments that integrates a MOSFET power device with an isolated gate?drive interface. The device is appropriate for implementation in dual?switch architecture. The diagram of TPSI2072?Q1 is in Figure 3-2.

Figure 3-2 Bidirectional SSR TPSI2072?Q1 Block Diagram

Below are key specifications to consider when using a solid?state relay for IMD:

• Isolation barrier: In using semiconductor technology, the TPSI2140?Q1 and TPSI2072?Q1 devices can potentially support over 26 years of isolation under 1000Vrms AC or 1500V DC.
• Standoff voltage: If the external voltage applied on an SSR is lower than the standoff voltage, only 1uA of leakage current flows from S1 to S2 or S2 to S1. Therese is no concern for a sticky contact when compared with traditional relays.
• Avalanche current: This specification is challenged in a Hi-pot test. During a Hi-pot test, ?2kV to 3kV apply on R_st and the SSR. Due to the 1.2kV standoff voltage of an SSR, R_st is required to limit the current and not exceed the avalanche current limitation of the SSR. The R_st selection is a trade-off in reliability and detection accuracy when considering Hi-pot testing.
• Turn ON/OFF time: A Y-capacitor significantly impacts settling time for a 50Hz or 60Hz system, based on the earlier analysis in Section 2. A Y-capacitor is helpful to suppress EMI in an OBC system, but a larger Y-capacitor leaves a shorter detection window for IMD. Therefore, the value of a Y-capacitor must be chosen carefully to have a balance between the benefits for EMI and the trade-offs for IMD during the design of the circuit.
• ON resistance: ON resistance impacts the accuracy of detection when the individual relay divides voltage from the main path.