3 UCC21520 Dynamic Characteristics

To evaluate the dynamic characteristics of the UCC21520, propagation delay, propagation delay matching and pulse width distortion performance are tested through different VDD voltage and temperature corners. For definition of these parameters, please refer to UCC21520 datasheet.

Figure 3 and Figure 4 show the propagation delay measurement data with temperature and VDD voltage corners. It can be seen that the propagation delay is independent of VDD voltage, and the typical propagation delay is less than 20 ns across wide temperature range, which helps to improve system response for high frequency applications, for example, timing control of zero voltage switching (ZVS), fast response for system protection, etc.

Figure 5 and Figure 6 show the propagation delay matching measurement data at temperature and VDD voltage corners. It can be seen that the delay matching at both the rising and falling edges is less than 2 ns within wide temperature and VDD ranges, which does help the channel parallel performance to drive large capacitance load.

Figure 7 and Figure 8 shows the pulse width distortion (PWD) measurement data, and it is less than 1 ns through all the temperature and VDD voltage corners. Low PWD does help deliver the correct and precise response with the given input signal, and maintain stable system operation.

In summary, low propagation delay, low propagation delay matching and low pulse width distortion does position the UCC21520 as the best-in-class gate driver with the best-in-class dynamic response. It is important to note that less than 2-ns propagation delay matching help to parallel the two output channels, double the gate drive strength and increase the versatility of the UCC21520 for a variety of applications.