ZHCSQ75C June 2022 – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
- 9.2.2.2 Primary Magnetizing Inductance of the Flyback Transformer (LM)
- 9.2.2.3 Number of Turns of the Flyback Transformer Windings
- 9.2.2.4 Current Sense Resistors (R24, R25) and Current Limiting
- 9.2.2.5 Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
- 9.2.2.6 Primary-Side Current Stress and Input Capacitor Selection
- 9.2.2.7 Secondary-Side Current Stress and Output Capacitor Selection
- 9.2.2.8 VDD Capacitors (C12, C18)
- 9.2.2.9 Gate Drive Network (R14, R16, Q6)
- 9.2.2.10 VREF Capacitor (C18)
- 9.2.2.11 RT/CT Components (R12, C15)
- 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
- 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
- 9.2.2.14 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.3 PCB Layout Recommendations
- 9.4 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.3.7 Soft Start
Soft start is the technique to gradually power up the converter in a well-controlled fashion by slowly increasing the effective duty cycle starting at zero and gradually rising. Following start-up of the PWM, the error amplifier inverting input is low, commanding the error amplifier’s output to go high. The output stage of the amplifier can source 1 mA typically, which is enough to drive most high impedance compensation networks, but not enough for driving large loads quickly. Soft start is achieved by charging a fairly large value, >1-μF, capacitor (CSS) connected to the error amplifier output through a PNP transistor as shown in Figure 8-6
Figure 8-6 Soft-Start
ImplementationThe limited charging current of the amplifier into the capacitor translates into a dv/dt limitation on the error amplifier output. This directly corresponds to some maximum rate of change of primary current in a current mode controlled system as one of the PWM comparator’s inputs gradually rises. The values of RSS and CSS must be selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power stage. After the soft-start interval is complete, the capacitor continues to charge to VREF, effectively removing the PNP transistor from the circuit consideration. Soft start performs a different, frequently preferred function in current mode controlled systems than it does in voltage mode control. In current mode, soft start controls the rising of the peak switch current. In voltage mode control, soft start gradually widens the duty cycle, regardless of the primary current or rate of ramp-up.
The purpose of the resistor RSS and diode is to take the soft-start capacitor out of the error amplifier’s path during normal operation, once soft start is complete and the capacitor is fully charged. The optional diode in parallel with the resistor forces a soft start each time the PWM goes through UVLO condition that forces VREF to go low. Without the diode, the capacitor remains charged during a brief loss of supply or brown-out, and no soft start is enabled upon re-application of VDD.