ZHCSQ75C June 2022 – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
- 9.2.2.2 Primary Magnetizing Inductance of the Flyback Transformer (LM)
- 9.2.2.3 Number of Turns of the Flyback Transformer Windings
- 9.2.2.4 Current Sense Resistors (R24, R25) and Current Limiting
- 9.2.2.5 Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
- 9.2.2.6 Primary-Side Current Stress and Input Capacitor Selection
- 9.2.2.7 Secondary-Side Current Stress and Output Capacitor Selection
- 9.2.2.8 VDD Capacitors (C12, C18)
- 9.2.2.9 Gate Drive Network (R14, R16, Q6)
- 9.2.2.10 VREF Capacitor (C18)
- 9.2.2.11 RT/CT Components (R12, C15)
- 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
- 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
- 9.2.2.14 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.3 PCB Layout Recommendations
- 9.4 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.2.2.14.2 Compensation Components
To compensate a peak-current-mode controller it’s very common to use a Type-II compensator. The Type-II compensator introduces a pole at DC, a relatively low frequency zero (fZ,COMP), and a higher frequency pole (fP,COMP). The pole at DC forces the system to have high gain at very low frequency and zero stead-state error.
Figure 9-4 Type-II Compensation with an
Error AmplifierThe low frequency zero is formed by R18 and C19
The higher frequency pole is formed by R18 and C20
The mid-frequency gain of the compensator is given by
First, select a crossover frequency, 625 Hz. Then, use the frequency response of the plant (control-to-output) at low input voltage to determine how much gain the compensator must add to increase the crossover to the desired bandwidth. In Figure 9-5 the plant is measured to be -23.3 dB at 625 Hz. Therefore, the error amplifier must have a mid-frequency gain of 14.6 V/V.
Figure 9-5 Measuring the plant gain at
the desired crossover frequency: -23 dB at 625 HzChoose (R17+R19) = 22.5 k?, and solve for R18
Select a standard value for R18, like 324 k?.
Now that we know R18, it’s fairly straightforward to set fZ,COMP = fPOLE and solve for C19
Likewise, set fP,COMP = fZERO and solve the following for C20
Finally, choose standard capacitor values, C19 = 22 nF and C20 = 100 pF. Notice that a slightly lower value was used for C19 than calculated. This was done to have a faster “reset” time during after a load transient response. If the complete loop is found to have too little phase margin then C19 can be increased at the cost of slower reset time.