ZHCSQ75C June 2022 – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
- 9.2.2.2 Primary Magnetizing Inductance of the Flyback Transformer (LM)
- 9.2.2.3 Number of Turns of the Flyback Transformer Windings
- 9.2.2.4 Current Sense Resistors (R24, R25) and Current Limiting
- 9.2.2.5 Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
- 9.2.2.6 Primary-Side Current Stress and Input Capacitor Selection
- 9.2.2.7 Secondary-Side Current Stress and Output Capacitor Selection
- 9.2.2.8 VDD Capacitors (C12, C18)
- 9.2.2.9 Gate Drive Network (R14, R16, Q6)
- 9.2.2.10 VREF Capacitor (C18)
- 9.2.2.11 RT/CT Components (R12, C15)
- 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
- 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
- 9.2.2.14 Voltage Feedback Compensation
- 9.2.3 Application Curves
- 9.3 PCB Layout Recommendations
- 9.4 Power Supply Recommendations
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
8.3.2 Undervoltage Lockout
Six sets of UVLO thresholds are available with turn-on and turnoff thresholds of: (14.5 V and 9 V), (8.4 V and 7.6 V), (7 V and 6.6 V), (18.8 V and 15.5 V), (18.8 V and 14.5V) and (16 V and 12.5V), respectively. The first set is primarily intended for off-line and 48-V distributed power applications, where the wider hysteresis allows for lower frequency operation and longer soft-starting time of the converter. The second set of UVLO option is ideal for high frequency DC-DC converters typically running from a 12-VDC input. The third set is for battery powered and portable applications. The fourth to sixth UVLO sets are to drive SiC MOSFETs in High Voltage applications. Table 8-2 shows the maximum duty cycle and UVLO thresholds by device.
| MAXIMUM DUTY CYCLE | UVLO ON | UVLO OFF | PART NUMBER |
|---|---|---|---|
| 100% | 14.5 V | 9 V | UCC28C52-Q1 |
| 100% | 8.4 V | 7.6 V | UCC28C53-Q1 |
| 100% | 7 V | 6.6 V | UCC28C50-Q1 |
|
100% |
18.8 V |
15.5 V |
UCC28C56H-Q1 |
|
100% |
18.8 V |
14.5 V |
UCC28C56L-Q1 |
|
100% |
16 V |
12.5 V |
UCC28C58-Q1 |
| 50% | 14.5 V | 9 V | UCC28C54-Q1 |
| 50% | 8.4 V | 7.6 V | UCC28C55-Q1 |
| 50% | 7 V | 6.6 V | UCC28C51-Q1 |
|
50% |
18.8 V |
15.5 V |
UCC28C57H-Q1 |
|
50% |
18.8 V |
14.5 V |
UCC28C57L-Q1 |
|
50% |
16 V |
12.5 V |
UCC28C59-Q1 |
During UVLO the device draws less than 75 μA of supply current. Once crossing the turn-on threshold the device supply current increases to a maximum of 2 mA, typically 1.3 mA. This low start-up current allows the power supply designer to optimize the selection of the start-up resistor value to provide a more efficient design. In applications where low component cost overrides maximum efficiency, the low run current of 1.3 mA (typical) allows the control device to run directly through the single resistor to (+) rail, rather than requiring a bootstrap winding on the power transformer, along with a rectifier. The start and run resistor for this case must also pass enough current to allow driving the primary switching MOSFET, which may be a few milliamps in small devices.
Figure 8-2 UVLO ON and OFF
Profile