ZHCSLD2E may 2020 – july 2023 UCC28782
PRODUCTION DATA
Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation delays of their drivers, the SET pin is provided to program critical parameters of UCC28782 for the two different power stages. Firstly, this pin sets the zero voltage threshold (VTH(SWS)) at the SWS input pin to be two different auto-tuning targets for ZVS control. When SET pin is tied to AGND, VTH(SWS) is set at its low level of 4 V for realizing full ZVS, which allows the low-side switch (QL) to be turned on when the switch-node voltage drops close to 0 V. When SET pin is tied to REF pin, VTH(SWS) is set at 8.5 V for implementing partial ZVS, which makes QL turn on at around 8.5 V. Secondly, the SET pin also selects the current sense leading edge blanking time (tCSLEB) to accommodate different delays of the gate drivers; 110 ns for VSET = 0 V and 190 ns for VSET = 5 V. Thirdly, the minimum PWML on-time (tON(MIN)) in low-power mode and standby-power mode is 110 ns for VSET = 0 V, and is 100 ns for VSET = 5 V. Finally, the maximum PWML on-time to detect CS pin fault (tCSF). tCSF for VSET = 5 V (tCSF1) is set at 2 μs. tCSF for VSET = 0 V (tCSF0) depends on RRDM, which is configured to 1 μs under RRDM < RRDM(TH) and to 2 μs under RRDM ≥ RRDM(TH).